NXP Semiconductors
MKL04Z4
2024.06.02
MKL04Z4 Freescale Microcontroller
CM0PLUS
r0p0
little
2
false
8
32
ADC0
Analog-to-Digital Converter
ADC0
0x0
0x0
0x50
registers
n
ADC0
15
INT_ADC0
15
CFG1
ADC Configuration Register 1
0x8
32
read-write
n
0x0
0x0
ADICLK
Input Clock Select
0
2
read-write
00
Bus clock
#00
01
(Bus clock)/2
#01
10
Alternate clock (ALTCLK)
#10
11
Asynchronous clock (ADACK)
#11
ADIV
Clock Divide Select
5
2
read-write
00
The divide ratio is 1 and the clock rate is input clock.
#00
01
The divide ratio is 2 and the clock rate is (input clock)/2.
#01
10
The divide ratio is 4 and the clock rate is (input clock)/4.
#10
11
The divide ratio is 8 and the clock rate is (input clock)/8.
#11
ADLPC
Low-Power Configuration
7
1
read-write
0
Normal power configuration.
#0
1
Low-power configuration. The power is reduced at the expense of maximum clock speed.
#1
ADLSMP
Sample time configuration
4
1
read-write
0
Short sample time.
#0
1
Long sample time.
#1
MODE
Conversion mode selection
2
2
read-write
00
It is single-ended 8-bit conversion.
#00
01
It is single-ended 12-bit conversion .
#01
10
It is single-ended 10-bit conversion .
#10
11
Reserved. Do not set the bitfield to this value.
#11
RESERVED
no description available
8
24
read-only
CFG2
ADC Configuration Register 2
0xC
32
read-write
n
0x0
0x0
ADACKEN
Asynchronous Clock Output Enable
3
1
read-write
0
Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.
#0
1
Asynchronous clock and clock output is enabled regardless of the state of the ADC.
#1
ADHSC
High-Speed Configuration
2
1
read-write
0
Normal conversion sequence selected.
#0
1
High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
#1
ADLSTS
Long Sample Time Select
0
2
read-write
00
Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
#00
01
12 extra ADCK cycles; 16 ADCK cycles total sample time.
#01
10
6 extra ADCK cycles; 10 ADCK cycles total sample time.
#10
11
2 extra ADCK cycles; 6 ADCK cycles total sample time.
#11
MUXSEL
ADC Mux Select
4
1
read-write
0
ADxxa channels are selected.
#0
1
ADxxb channels are selected.
#1
RESERVED
no description available
5
3
read-only
RESERVED
no description available
8
24
read-only
CLP0
ADC Plus-Side General Calibration Value Register
0x4C
32
read-write
n
0x0
0x0
CLP0
no description available
0
6
read-write
RESERVED
no description available
6
26
read-only
CLP1
ADC Plus-Side General Calibration Value Register
0x48
32
read-write
n
0x0
0x0
CLP1
no description available
0
7
read-write
RESERVED
no description available
7
25
read-only
CLP2
ADC Plus-Side General Calibration Value Register
0x44
32
read-write
n
0x0
0x0
CLP2
no description available
0
8
read-write
RESERVED
no description available
8
24
read-only
CLP3
ADC Plus-Side General Calibration Value Register
0x40
32
read-write
n
0x0
0x0
CLP3
no description available
0
9
read-write
RESERVED
no description available
9
23
read-only
CLP4
ADC Plus-Side General Calibration Value Register
0x3C
32
read-write
n
0x0
0x0
CLP4
no description available
0
10
read-write
RESERVED
no description available
10
22
read-only
CLPD
ADC Plus-Side General Calibration Value Register
0x34
32
read-write
n
0x0
0x0
CLPD
no description available
0
6
read-write
RESERVED
no description available
6
26
read-only
CLPS
ADC Plus-Side General Calibration Value Register
0x38
32
read-write
n
0x0
0x0
CLPS
no description available
0
6
read-write
RESERVED
no description available
6
26
read-only
CV1
Compare Value Registers
0x30
32
read-write
n
0x0
0x0
CV
Compare Value.
0
16
read-write
RESERVED
no description available
16
16
read-only
CV2
Compare Value Registers
0x4C
32
read-write
n
0x0
0x0
CV
Compare Value.
0
16
read-write
RESERVED
no description available
16
16
read-only
OFS
ADC Offset Correction Register
0x28
32
read-write
n
0x0
0x0
OFS
Offset Error Correction Value
0
16
read-write
RESERVED
no description available
16
16
read-only
PG
ADC Plus-Side Gain Register
0x2C
32
read-write
n
0x0
0x0
PG
Plus-Side Gain
0
16
read-write
RESERVED
no description available
16
16
read-only
RA
ADC Data Result Register
0x20
32
read-only
n
0x0
0x0
D
Data result
0
16
read-only
RESERVED
no description available
16
16
read-only
RB
ADC Data Result Register
0x34
32
read-only
n
0x0
0x0
D
Data result
0
16
read-only
RESERVED
no description available
16
16
read-only
SC1A
ADC Status and Control Registers 1
0x0
32
read-write
n
0x0
0x0
ADCH
Input channel select
0
5
read-write
00000
AD0 is selected as input.
#00000
00001
AD1 is selected as input.
#00001
00010
AD2 is selected as input.
#00010
00011
AD3 is selected as input.
#00011
00100
AD4 is selected as input.
#00100
00101
AD5 is selected as input.
#00101
00110
AD6 is selected as input.
#00110
00111
AD7 is selected as input.
#00111
01000
AD8 is selected as input.
#01000
01001
AD9 is selected as input.
#01001
01010
AD10 is selected as input.
#01010
01011
AD11 is selected as input.
#01011
01100
AD12 is selected as input.
#01100
01101
AD13 is selected as input.
#01101
01110
AD14 is selected as input.
#01110
01111
AD15 is selected as input.
#01111
10000
AD16 is selected as input.
#10000
10001
AD17 is selected as input.
#10001
10010
AD18 is selected as input.
#10010
10011
AD19 is selected as input.
#10011
10100
AD20 is selected as input.
#10100
10101
AD21 is selected as input.
#10101
10110
AD22 is selected as input.
#10110
10111
AD23 is selected as input.
#10111
11000
Reserved.
#11000
11001
Reserved.
#11001
11010
Temp Sensor (single-ended) is selected as input.
#11010
11011
Bandgap (single-ended) is selected as input.
#11011
11100
Reserved.
#11100
11101
VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL].
#11101
11110
VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL].
#11110
11111
Module is disabled.
#11111
AIEN
Interrupt Enable
6
1
read-write
0
Conversion complete interrupt is disabled.
#0
1
Conversion complete interrupt is enabled.
#1
COCO
Conversion Complete Flag
7
1
read-only
0
Conversion is not completed.
#0
1
Conversion is completed.
#1
RESERVED
no description available
5
1
read-only
RESERVED
no description available
8
24
read-only
SC1B
ADC Status and Control Registers 1
0x4
32
read-write
n
0x0
0x0
ADCH
Input channel select
0
5
read-write
00000
AD0 is selected as input.
#00000
00001
AD1 is selected as input.
#00001
00010
AD2 is selected as input.
#00010
00011
AD3 is selected as input.
#00011
00100
AD4 is selected as input.
#00100
00101
AD5 is selected as input.
#00101
00110
AD6 is selected as input.
#00110
00111
AD7 is selected as input.
#00111
01000
AD8 is selected as input.
#01000
01001
AD9 is selected as input.
#01001
01010
AD10 is selected as input.
#01010
01011
AD11 is selected as input.
#01011
01100
AD12 is selected as input.
#01100
01101
AD13 is selected as input.
#01101
01110
AD14 is selected as input.
#01110
01111
AD15 is selected as input.
#01111
10000
AD16 is selected as input.
#10000
10001
AD17 is selected as input.
#10001
10010
AD18 is selected as input.
#10010
10011
AD19 is selected as input.
#10011
10100
AD20 is selected as input.
#10100
10101
AD21 is selected as input.
#10101
10110
AD22 is selected as input.
#10110
10111
AD23 is selected as input.
#10111
11000
Reserved.
#11000
11001
Reserved.
#11001
11010
Temp Sensor (single-ended) is selected as input.
#11010
11011
Bandgap (single-ended) is selected as input.
#11011
11100
Reserved.
#11100
11101
VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL].
#11101
11110
VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL].
#11110
11111
Module is disabled.
#11111
AIEN
Interrupt Enable
6
1
read-write
0
Conversion complete interrupt is disabled.
#0
1
Conversion complete interrupt is enabled.
#1
COCO
Conversion Complete Flag
7
1
read-only
0
Conversion is not completed.
#0
1
Conversion is completed.
#1
RESERVED
no description available
5
1
read-only
RESERVED
no description available
8
24
read-only
SC2
Status and Control Register 2
0x20
32
read-write
n
0x0
0x0
ACFE
Compare Function Enable
5
1
read-write
0
Compare function disabled.
#0
1
Compare function enabled.
#1
ACFGT
Compare Function Greater Than Enable
4
1
read-write
0
Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.
#0
1
Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.
#1
ACREN
Compare Function Range Enable
3
1
read-write
0
Range function disabled. Only CV1 is compared.
#0
1
Range function enabled. Both CV1 and CV2 are compared.
#1
ADACT
Conversion Active
7
1
read-only
0
Conversion not in progress.
#0
1
Conversion in progress.
#1
ADTRG
Conversion Trigger Select
6
1
read-write
0
Software trigger selected.
#0
1
Hardware trigger selected.
#1
DMAEN
DMA Enable
2
1
read-write
0
DMA is disabled.
#0
1
DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.
#1
REFSEL
Voltage Reference Selection
0
2
read-write
00
Default voltage reference pin pair, that is, external pins VREFH and VREFL
#00
01
Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU
#01
10
Reserved
#10
11
Reserved
#11
RESERVED
no description available
8
24
read-only
SC3
Status and Control Register 3
0x24
32
read-write
n
0x0
0x0
ADCO
Continuous Conversion Enable
3
1
read-write
0
One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
#0
1
Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
#1
AVGE
Hardware Average Enable
2
1
read-write
0
Hardware average function disabled.
#0
1
Hardware average function enabled.
#1
AVGS
Hardware Average Select
0
2
read-write
00
4 samples averaged.
#00
01
8 samples averaged.
#01
10
16 samples averaged.
#10
11
32 samples averaged.
#11
CAL
Calibration
7
1
read-write
CALF
Calibration Failed Flag
6
1
read-only
0
Calibration completed normally.
#0
1
Calibration failed. ADC accuracy specifications are not guaranteed.
#1
RESERVED
no description available
4
2
read-only
RESERVED
no description available
8
24
read-only
CMP0
High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
CMP0
0x0
0x0
0x6
registers
n
CMP0
16
INT_CMP0
16
CR0
CMP Control Register 0
0x0
8
read-write
n
0x0
0x0
FILTER_CNT
Filter Sample Count
4
3
read-write
000
Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
#000
001
One sample must agree. The comparator output is simply sampled.
#001
010
2 consecutive samples must agree.
#010
011
3 consecutive samples must agree.
#011
100
4 consecutive samples must agree.
#100
101
5 consecutive samples must agree.
#101
110
6 consecutive samples must agree.
#110
111
7 consecutive samples must agree.
#111
HYSTCTR
Comparator hard block hysteresis control
0
2
read-write
00
Level 0
#00
01
Level 1
#01
10
Level 2
#10
11
Level 3
#11
RESERVED
no description available
2
1
read-only
RESERVED
no description available
3
1
read-only
RESERVED
no description available
7
1
read-only
CR1
CMP Control Register 1
0x1
8
read-write
n
0x0
0x0
COS
Comparator Output Select
2
1
read-write
0
Set the filtered comparator output (CMPO) to equal COUT.
#0
1
Set the unfiltered comparator output (CMPO) to equal COUTA.
#1
EN
Comparator Module Enable
0
1
read-write
0
Analog Comparator is disabled.
#0
1
Analog Comparator is enabled.
#1
INV
Comparator INVERT
3
1
read-write
0
Does not invert the comparator output.
#0
1
Inverts the comparator output.
#1
OPE
Comparator Output Pin Enable
1
1
read-write
0
CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
#0
1
CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.
#1
PMODE
Power Mode Select
4
1
read-write
0
Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
#0
1
High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
#1
SE
Sample Enable
7
1
read-write
0
Sampling mode is not selected.
#0
1
Sampling mode is selected.
#1
TRIGM
Trigger Mode Enable
5
1
read-write
0
Trigger mode is disabled.
#0
1
Trigger mode is enabled.
#1
WE
Windowing Enable
6
1
read-write
0
Windowing mode is not selected.
#0
1
Windowing mode is selected.
#1
DACCR
DAC Control Register
0x4
8
read-write
n
0x0
0x0
DACEN
DAC Enable
7
1
read-write
0
DAC is disabled.
#0
1
DAC is enabled.
#1
VOSEL
DAC Output Voltage Select
0
6
read-write
VRSEL
Supply Voltage Reference Source Select
6
1
read-write
0
V is selected as resistor ladder network supply reference V. in1 in
#0
1
V is selected as resistor ladder network supply reference V. in2 in
#1
FPR
CMP Filter Period Register
0x2
8
read-write
n
0x0
0x0
FILT_PER
Filter Sample Period
0
8
read-write
MUXCR
MUX Control Register
0x5
8
read-write
n
0x0
0x0
MSEL
Minus Input Mux Control
0
3
read-write
000
IN0
#000
001
IN1
#001
010
IN2
#010
011
IN3
#011
100
IN4
#100
101
IN5
#101
110
IN6
#110
111
IN7
#111
PSEL
Plus Input Mux Control
3
3
read-write
000
IN0
#000
001
IN1
#001
010
IN2
#010
011
IN3
#011
100
IN4
#100
101
IN5
#101
110
IN6
#110
111
IN7
#111
PSTM
Pass Through Mode Enable
7
1
read-write
0
Pass Through Mode is disabled.
#0
1
Pass Through Mode is enabled.
#1
RESERVED
no description available
6
1
read-only
SCR
CMP Status and Control Register
0x3
8
read-write
n
0x0
0x0
CFF
Analog Comparator Flag Falling
1
1
read-write
0
Falling-edge on COUT has not been detected.
#0
1
Falling-edge on COUT has occurred.
#1
CFR
Analog Comparator Flag Rising
2
1
read-write
0
Rising-edge on COUT has not been detected.
#0
1
Rising-edge on COUT has occurred.
#1
COUT
Analog Comparator Output
0
1
read-only
DMAEN
DMA Enable Control
6
1
read-write
0
DMA is disabled.
#0
1
DMA is enabled.
#1
IEF
Comparator Interrupt Enable Falling
3
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
IER
Comparator Interrupt Enable Rising
4
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
DMA
DMA Controller
DMA
0x0
0x100
0x40
registers
n
DMA0
0
INT_DMA0
0
DMA1
1
INT_DMA1
1
DMA2
2
INT_DMA2
2
DMA3
3
INT_DMA3
3
DAR0
Destination Address Register
0x208
32
read-write
n
0x0
0x0
DAR
no description available
0
32
read-write
DAR1
Destination Address Register
0x31C
32
read-write
n
0x0
0x0
DAR
no description available
0
32
read-write
DAR2
Destination Address Register
0x440
32
read-write
n
0x0
0x0
DAR
no description available
0
32
read-write
DAR3
Destination Address Register
0x574
32
read-write
n
0x0
0x0
DAR
no description available
0
32
read-write
DCR0
DMA Control Register
0x218
32
read-write
n
0x0
0x0
AA
Auto-align
28
1
read-write
0
Auto-align disabled
#0
1
If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
#1
CS
Cycle steal
29
1
read-write
0
DMA continuously makes read/write transfers until the BCR decrements to 0.
#0
1
Forces a single read/write transfer per request.
#1
DINC
Destination increment
19
1
read-write
0
No change to the DAR after a successful transfer.
#0
1
The DAR increments by 1, 2, 4 depending upon the size of the transfer.
#1
DMOD
Destination address modulo
8
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes
#0001
0010
Circular buffer size is 32 bytes
#0010
0011
Circular buffer size is 64 bytes
#0011
0100
Circular buffer size is 128 bytes
#0100
0101
Circular buffer size is 256 bytes
#0101
0110
Circular buffer size is 512 bytes
#0110
0111
Circular buffer size is 1 KB
#0111
1000
Circular buffer size is 2 KB
#1000
1001
Circular buffer size is 4 KB
#1001
1010
Circular buffer size is 8 KB
#1010
1011
Circular buffer size is 16 KB
#1011
1100
Circular buffer size is 32 KB
#1100
1101
Circular buffer size is 64 KB
#1101
1110
Circular buffer size is 128 KB
#1110
1111
Circular buffer size is 256 KB
#1111
DSIZE
Destination size
17
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
D_REQ
Disable request
7
1
read-write
0
ERQ bit is not affected.
#0
1
ERQ bit is cleared when the BCR is exhausted.
#1
EADREQ
Enable asynchronous DMA requests
23
1
read-write
0
Disabled
#0
1
Enabled
#1
EINT
Enable interrupt on completion of transfer
31
1
read-write
0
No interrupt is generated.
#0
1
Interrupt signal is enabled.
#1
ERQ
Enable peripheral request
30
1
read-write
0
Peripheral request is ignored.
#0
1
Enables peripheral request to initiate transfer. A software-initiated request (setting the START bit) is always enabled.
#1
LCH1
Link channel 1
2
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LCH2
Link channel 2
0
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LINKCC
Link channel control
4
2
read-write
00
No channel-to-channel linking
#00
01
Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to zero
#01
10
Perform a link to channel LCH1 after each cycle-steal transfer
#10
11
Perform a link to channel LCH1 after the BCR decrements to zero
#11
RESERVED
no description available
6
1
read-only
RESERVED
no description available
24
1
read-write
RESERVED
no description available
25
3
read-only
SINC
Source increment
22
1
read-write
0
No change to SAR after a successful transfer.
#0
1
The SAR increments by 1, 2, 4 as determined by the transfer size.
#1
SMOD
Source address modulo
12
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes
#0001
0010
Circular buffer size is 32 bytes
#0010
0011
Circular buffer size is 64 bytes
#0011
0100
Circular buffer size is 128 bytes
#0100
0101
Circular buffer size is 256 bytes
#0101
0110
Circular buffer size is 512 bytes
#0110
0111
Circular buffer size is 1 KB
#0111
1000
Circular buffer size is 2 KB
#1000
1001
Circular buffer size is 4 KB
#1001
1010
Circular buffer size is 8 KB
#1010
1011
Circular buffer size is 16 KB
#1011
1100
Circular buffer size is 32 KB
#1100
1101
Circular buffer size is 64 KB
#1101
1110
Circular buffer size is 128 KB
#1110
1111
Circular buffer size is 256 KB
#1111
SSIZE
Source size
20
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
START
Start transfer
16
1
write-only
0
DMA inactive
#0
1
The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
#1
DCR1
DMA Control Register
0x334
32
read-write
n
0x0
0x0
AA
Auto-align
28
1
read-write
0
Auto-align disabled
#0
1
If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
#1
CS
Cycle steal
29
1
read-write
0
DMA continuously makes read/write transfers until the BCR decrements to 0.
#0
1
Forces a single read/write transfer per request.
#1
DINC
Destination increment
19
1
read-write
0
No change to the DAR after a successful transfer.
#0
1
The DAR increments by 1, 2, 4 depending upon the size of the transfer.
#1
DMOD
Destination address modulo
8
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes
#0001
0010
Circular buffer size is 32 bytes
#0010
0011
Circular buffer size is 64 bytes
#0011
0100
Circular buffer size is 128 bytes
#0100
0101
Circular buffer size is 256 bytes
#0101
0110
Circular buffer size is 512 bytes
#0110
0111
Circular buffer size is 1 KB
#0111
1000
Circular buffer size is 2 KB
#1000
1001
Circular buffer size is 4 KB
#1001
1010
Circular buffer size is 8 KB
#1010
1011
Circular buffer size is 16 KB
#1011
1100
Circular buffer size is 32 KB
#1100
1101
Circular buffer size is 64 KB
#1101
1110
Circular buffer size is 128 KB
#1110
1111
Circular buffer size is 256 KB
#1111
DSIZE
Destination size
17
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
D_REQ
Disable request
7
1
read-write
0
ERQ bit is not affected.
#0
1
ERQ bit is cleared when the BCR is exhausted.
#1
EADREQ
Enable asynchronous DMA requests
23
1
read-write
0
Disabled
#0
1
Enabled
#1
EINT
Enable interrupt on completion of transfer
31
1
read-write
0
No interrupt is generated.
#0
1
Interrupt signal is enabled.
#1
ERQ
Enable peripheral request
30
1
read-write
0
Peripheral request is ignored.
#0
1
Enables peripheral request to initiate transfer. A software-initiated request (setting the START bit) is always enabled.
#1
LCH1
Link channel 1
2
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LCH2
Link channel 2
0
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LINKCC
Link channel control
4
2
read-write
00
No channel-to-channel linking
#00
01
Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to zero
#01
10
Perform a link to channel LCH1 after each cycle-steal transfer
#10
11
Perform a link to channel LCH1 after the BCR decrements to zero
#11
RESERVED
no description available
6
1
read-only
RESERVED
no description available
24
1
read-write
RESERVED
no description available
25
3
read-only
SINC
Source increment
22
1
read-write
0
No change to SAR after a successful transfer.
#0
1
The SAR increments by 1, 2, 4 as determined by the transfer size.
#1
SMOD
Source address modulo
12
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes
#0001
0010
Circular buffer size is 32 bytes
#0010
0011
Circular buffer size is 64 bytes
#0011
0100
Circular buffer size is 128 bytes
#0100
0101
Circular buffer size is 256 bytes
#0101
0110
Circular buffer size is 512 bytes
#0110
0111
Circular buffer size is 1 KB
#0111
1000
Circular buffer size is 2 KB
#1000
1001
Circular buffer size is 4 KB
#1001
1010
Circular buffer size is 8 KB
#1010
1011
Circular buffer size is 16 KB
#1011
1100
Circular buffer size is 32 KB
#1100
1101
Circular buffer size is 64 KB
#1101
1110
Circular buffer size is 128 KB
#1110
1111
Circular buffer size is 256 KB
#1111
SSIZE
Source size
20
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
START
Start transfer
16
1
write-only
0
DMA inactive
#0
1
The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
#1
DCR2
DMA Control Register
0x460
32
read-write
n
0x0
0x0
AA
Auto-align
28
1
read-write
0
Auto-align disabled
#0
1
If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
#1
CS
Cycle steal
29
1
read-write
0
DMA continuously makes read/write transfers until the BCR decrements to 0.
#0
1
Forces a single read/write transfer per request.
#1
DINC
Destination increment
19
1
read-write
0
No change to the DAR after a successful transfer.
#0
1
The DAR increments by 1, 2, 4 depending upon the size of the transfer.
#1
DMOD
Destination address modulo
8
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes
#0001
0010
Circular buffer size is 32 bytes
#0010
0011
Circular buffer size is 64 bytes
#0011
0100
Circular buffer size is 128 bytes
#0100
0101
Circular buffer size is 256 bytes
#0101
0110
Circular buffer size is 512 bytes
#0110
0111
Circular buffer size is 1 KB
#0111
1000
Circular buffer size is 2 KB
#1000
1001
Circular buffer size is 4 KB
#1001
1010
Circular buffer size is 8 KB
#1010
1011
Circular buffer size is 16 KB
#1011
1100
Circular buffer size is 32 KB
#1100
1101
Circular buffer size is 64 KB
#1101
1110
Circular buffer size is 128 KB
#1110
1111
Circular buffer size is 256 KB
#1111
DSIZE
Destination size
17
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
D_REQ
Disable request
7
1
read-write
0
ERQ bit is not affected.
#0
1
ERQ bit is cleared when the BCR is exhausted.
#1
EADREQ
Enable asynchronous DMA requests
23
1
read-write
0
Disabled
#0
1
Enabled
#1
EINT
Enable interrupt on completion of transfer
31
1
read-write
0
No interrupt is generated.
#0
1
Interrupt signal is enabled.
#1
ERQ
Enable peripheral request
30
1
read-write
0
Peripheral request is ignored.
#0
1
Enables peripheral request to initiate transfer. A software-initiated request (setting the START bit) is always enabled.
#1
LCH1
Link channel 1
2
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LCH2
Link channel 2
0
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LINKCC
Link channel control
4
2
read-write
00
No channel-to-channel linking
#00
01
Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to zero
#01
10
Perform a link to channel LCH1 after each cycle-steal transfer
#10
11
Perform a link to channel LCH1 after the BCR decrements to zero
#11
RESERVED
no description available
6
1
read-only
RESERVED
no description available
24
1
read-write
RESERVED
no description available
25
3
read-only
SINC
Source increment
22
1
read-write
0
No change to SAR after a successful transfer.
#0
1
The SAR increments by 1, 2, 4 as determined by the transfer size.
#1
SMOD
Source address modulo
12
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes
#0001
0010
Circular buffer size is 32 bytes
#0010
0011
Circular buffer size is 64 bytes
#0011
0100
Circular buffer size is 128 bytes
#0100
0101
Circular buffer size is 256 bytes
#0101
0110
Circular buffer size is 512 bytes
#0110
0111
Circular buffer size is 1 KB
#0111
1000
Circular buffer size is 2 KB
#1000
1001
Circular buffer size is 4 KB
#1001
1010
Circular buffer size is 8 KB
#1010
1011
Circular buffer size is 16 KB
#1011
1100
Circular buffer size is 32 KB
#1100
1101
Circular buffer size is 64 KB
#1101
1110
Circular buffer size is 128 KB
#1110
1111
Circular buffer size is 256 KB
#1111
SSIZE
Source size
20
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
START
Start transfer
16
1
write-only
0
DMA inactive
#0
1
The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
#1
DCR3
DMA Control Register
0x59C
32
read-write
n
0x0
0x0
AA
Auto-align
28
1
read-write
0
Auto-align disabled
#0
1
If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
#1
CS
Cycle steal
29
1
read-write
0
DMA continuously makes read/write transfers until the BCR decrements to 0.
#0
1
Forces a single read/write transfer per request.
#1
DINC
Destination increment
19
1
read-write
0
No change to the DAR after a successful transfer.
#0
1
The DAR increments by 1, 2, 4 depending upon the size of the transfer.
#1
DMOD
Destination address modulo
8
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes
#0001
0010
Circular buffer size is 32 bytes
#0010
0011
Circular buffer size is 64 bytes
#0011
0100
Circular buffer size is 128 bytes
#0100
0101
Circular buffer size is 256 bytes
#0101
0110
Circular buffer size is 512 bytes
#0110
0111
Circular buffer size is 1 KB
#0111
1000
Circular buffer size is 2 KB
#1000
1001
Circular buffer size is 4 KB
#1001
1010
Circular buffer size is 8 KB
#1010
1011
Circular buffer size is 16 KB
#1011
1100
Circular buffer size is 32 KB
#1100
1101
Circular buffer size is 64 KB
#1101
1110
Circular buffer size is 128 KB
#1110
1111
Circular buffer size is 256 KB
#1111
DSIZE
Destination size
17
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
D_REQ
Disable request
7
1
read-write
0
ERQ bit is not affected.
#0
1
ERQ bit is cleared when the BCR is exhausted.
#1
EADREQ
Enable asynchronous DMA requests
23
1
read-write
0
Disabled
#0
1
Enabled
#1
EINT
Enable interrupt on completion of transfer
31
1
read-write
0
No interrupt is generated.
#0
1
Interrupt signal is enabled.
#1
ERQ
Enable peripheral request
30
1
read-write
0
Peripheral request is ignored.
#0
1
Enables peripheral request to initiate transfer. A software-initiated request (setting the START bit) is always enabled.
#1
LCH1
Link channel 1
2
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LCH2
Link channel 2
0
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LINKCC
Link channel control
4
2
read-write
00
No channel-to-channel linking
#00
01
Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to zero
#01
10
Perform a link to channel LCH1 after each cycle-steal transfer
#10
11
Perform a link to channel LCH1 after the BCR decrements to zero
#11
RESERVED
no description available
6
1
read-only
RESERVED
no description available
24
1
read-write
RESERVED
no description available
25
3
read-only
SINC
Source increment
22
1
read-write
0
No change to SAR after a successful transfer.
#0
1
The SAR increments by 1, 2, 4 as determined by the transfer size.
#1
SMOD
Source address modulo
12
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes
#0001
0010
Circular buffer size is 32 bytes
#0010
0011
Circular buffer size is 64 bytes
#0011
0100
Circular buffer size is 128 bytes
#0100
0101
Circular buffer size is 256 bytes
#0101
0110
Circular buffer size is 512 bytes
#0110
0111
Circular buffer size is 1 KB
#0111
1000
Circular buffer size is 2 KB
#1000
1001
Circular buffer size is 4 KB
#1001
1010
Circular buffer size is 8 KB
#1010
1011
Circular buffer size is 16 KB
#1011
1100
Circular buffer size is 32 KB
#1100
1101
Circular buffer size is 64 KB
#1101
1110
Circular buffer size is 128 KB
#1110
1111
Circular buffer size is 256 KB
#1111
SSIZE
Source size
20
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
START
Start transfer
16
1
write-only
0
DMA inactive
#0
1
The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
#1
DSR0
DMA_DSR0 register.
0x10B
8
read-write
n
0x0
0x0
RESERVED
Transactions done.
0
1
read-write
0
DMA transfer is not yet complete.
#0
1
DMA transfer completed.
#1
RESERVED
Busy.
1
1
read-only
0
DMA channel is inactive.
#0
1
BSY is set the first time the channel is enabled after a transfer is initiated.
#1
RESERVED
Request.
2
1
read-only
0
No request is pending or the channel is currently active.
#0
1
The DMA channel has a transfer remaining and the channel is not selected.
#1
RESERVED
no description available
3
1
read-only
RESERVED
Bus error on destination.
4
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the write portion of a transfer.
#1
RESERVED
Bus error on source.
5
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the read portion of a transfer.
#1
RESERVED
Configuration error.
6
1
read-only
0
No configuration error exists.
#0
1
A configuration error has occurred.
#1
RESERVED
no description available
7
1
read-only
DSR1
DMA_DSR1 register.
0x11B
8
read-write
n
0x0
0x0
RESERVED
Transactions done.
0
1
read-write
0
DMA transfer is not yet complete.
#0
1
DMA transfer completed.
#1
RESERVED
Busy.
1
1
read-only
0
DMA channel is inactive.
#0
1
BSY is set the first time the channel is enabled after a transfer is initiated.
#1
RESERVED
Request.
2
1
read-only
0
No request is pending or the channel is currently active.
#0
1
The DMA channel has a transfer remaining and the channel is not selected.
#1
RESERVED
no description available
3
1
read-only
RESERVED
Bus error on destination.
4
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the write portion of a transfer.
#1
RESERVED
Bus error on source.
5
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the read portion of a transfer.
#1
RESERVED
Configuration error.
6
1
read-only
0
No configuration error exists.
#0
1
A configuration error has occurred.
#1
RESERVED
no description available
7
1
read-only
DSR2
DMA_DSR2 register.
0x12B
8
read-write
n
0x0
0x0
RESERVED
Transactions done.
0
1
read-write
0
DMA transfer is not yet complete.
#0
1
DMA transfer completed.
#1
RESERVED
Busy.
1
1
read-only
0
DMA channel is inactive.
#0
1
BSY is set the first time the channel is enabled after a transfer is initiated.
#1
RESERVED
Request.
2
1
read-only
0
No request is pending or the channel is currently active.
#0
1
The DMA channel has a transfer remaining and the channel is not selected.
#1
RESERVED
no description available
3
1
read-only
RESERVED
Bus error on destination.
4
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the write portion of a transfer.
#1
RESERVED
Bus error on source.
5
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the read portion of a transfer.
#1
RESERVED
Configuration error.
6
1
read-only
0
No configuration error exists.
#0
1
A configuration error has occurred.
#1
RESERVED
no description available
7
1
read-only
DSR3
DMA_DSR3 register.
0x13B
8
read-write
n
0x0
0x0
RESERVED
Transactions done.
0
1
read-write
0
DMA transfer is not yet complete.
#0
1
DMA transfer completed.
#1
RESERVED
Busy.
1
1
read-only
0
DMA channel is inactive.
#0
1
BSY is set the first time the channel is enabled after a transfer is initiated.
#1
RESERVED
Request.
2
1
read-only
0
No request is pending or the channel is currently active.
#0
1
The DMA channel has a transfer remaining and the channel is not selected.
#1
RESERVED
no description available
3
1
read-only
RESERVED
Bus error on destination.
4
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the write portion of a transfer.
#1
RESERVED
Bus error on source.
5
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the read portion of a transfer.
#1
RESERVED
Configuration error.
6
1
read-only
0
No configuration error exists.
#0
1
A configuration error has occurred.
#1
RESERVED
no description available
7
1
read-only
DSR_BCR0
DMA Status Register / Byte Count Register
0x210
32
read-write
n
0x0
0x0
BCR
no description available
0
24
read-write
BED
Bus error on destination
28
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the write portion of a transfer.
#1
BES
Bus error on source
29
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the read portion of a transfer.
#1
BSY
Busy
25
1
read-only
0
DMA channel is inactive. Cleared when the DMA has finished the last transaction.
#0
1
BSY is set the first time the channel is enabled after a transfer is initiated.
#1
CE
Configuration error
30
1
read-only
0
No configuration error exists.
#0
1
A configuration error has occurred.
#1
DONE
Transactions done
24
1
read-write
0
DMA transfer is not yet complete. Writing a 0 has no effect.
#0
1
DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.
#1
REQ
Request
26
1
read-only
0
No request is pending or the channel is currently active. Cleared when the channel is selected.
#0
1
The DMA channel has a transfer remaining and the channel is not selected.
#1
RESERVED
no description available
27
1
read-only
RESERVED
no description available
31
1
read-only
DSR_BCR1
DMA Status Register / Byte Count Register
0x328
32
read-write
n
0x0
0x0
BCR
no description available
0
24
read-write
BED
Bus error on destination
28
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the write portion of a transfer.
#1
BES
Bus error on source
29
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the read portion of a transfer.
#1
BSY
Busy
25
1
read-only
0
DMA channel is inactive. Cleared when the DMA has finished the last transaction.
#0
1
BSY is set the first time the channel is enabled after a transfer is initiated.
#1
CE
Configuration error
30
1
read-only
0
No configuration error exists.
#0
1
A configuration error has occurred.
#1
DONE
Transactions done
24
1
read-write
0
DMA transfer is not yet complete. Writing a 0 has no effect.
#0
1
DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.
#1
REQ
Request
26
1
read-only
0
No request is pending or the channel is currently active. Cleared when the channel is selected.
#0
1
The DMA channel has a transfer remaining and the channel is not selected.
#1
RESERVED
no description available
27
1
read-only
RESERVED
no description available
31
1
read-only
DSR_BCR2
DMA Status Register / Byte Count Register
0x450
32
read-write
n
0x0
0x0
BCR
no description available
0
24
read-write
BED
Bus error on destination
28
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the write portion of a transfer.
#1
BES
Bus error on source
29
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the read portion of a transfer.
#1
BSY
Busy
25
1
read-only
0
DMA channel is inactive. Cleared when the DMA has finished the last transaction.
#0
1
BSY is set the first time the channel is enabled after a transfer is initiated.
#1
CE
Configuration error
30
1
read-only
0
No configuration error exists.
#0
1
A configuration error has occurred.
#1
DONE
Transactions done
24
1
read-write
0
DMA transfer is not yet complete. Writing a 0 has no effect.
#0
1
DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.
#1
REQ
Request
26
1
read-only
0
No request is pending or the channel is currently active. Cleared when the channel is selected.
#0
1
The DMA channel has a transfer remaining and the channel is not selected.
#1
RESERVED
no description available
27
1
read-only
RESERVED
no description available
31
1
read-only
DSR_BCR3
DMA Status Register / Byte Count Register
0x588
32
read-write
n
0x0
0x0
BCR
no description available
0
24
read-write
BED
Bus error on destination
28
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the write portion of a transfer.
#1
BES
Bus error on source
29
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the read portion of a transfer.
#1
BSY
Busy
25
1
read-only
0
DMA channel is inactive. Cleared when the DMA has finished the last transaction.
#0
1
BSY is set the first time the channel is enabled after a transfer is initiated.
#1
CE
Configuration error
30
1
read-only
0
No configuration error exists.
#0
1
A configuration error has occurred.
#1
DONE
Transactions done
24
1
read-write
0
DMA transfer is not yet complete. Writing a 0 has no effect.
#0
1
DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.
#1
REQ
Request
26
1
read-only
0
No request is pending or the channel is currently active. Cleared when the channel is selected.
#0
1
The DMA channel has a transfer remaining and the channel is not selected.
#1
RESERVED
no description available
27
1
read-only
RESERVED
no description available
31
1
read-only
SAR0
Source Address Register
0x200
32
read-write
n
0x0
0x0
SAR
no description available
0
32
read-write
SAR1
Source Address Register
0x310
32
read-write
n
0x0
0x0
SAR
no description available
0
32
read-write
SAR2
Source Address Register
0x430
32
read-write
n
0x0
0x0
SAR
no description available
0
32
read-write
SAR3
Source Address Register
0x560
32
read-write
n
0x0
0x0
SAR
no description available
0
32
read-write
DMAMUX0
DMA channel multiplexor
DMAMUX0
0x0
0x0
0x4
registers
n
CHCFG0
Channel Configuration register
0x0
8
read-write
n
0x0
0x0
ENBL
DMA Channel Enable
7
1
read-write
0
DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
#0
1
DMA channel is enabled
#1
SOURCE
DMA Channel Source (Slot)
0
6
read-write
TRIG
DMA Channel Trigger Enable
6
1
read-write
0
Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#0
1
Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in Periodic Trigger mode.
#1
CHCFG1
Channel Configuration register
0x1
8
read-write
n
0x0
0x0
ENBL
DMA Channel Enable
7
1
read-write
0
DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
#0
1
DMA channel is enabled
#1
SOURCE
DMA Channel Source (Slot)
0
6
read-write
TRIG
DMA Channel Trigger Enable
6
1
read-write
0
Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#0
1
Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in Periodic Trigger mode.
#1
CHCFG2
Channel Configuration register
0x3
8
read-write
n
0x0
0x0
ENBL
DMA Channel Enable
7
1
read-write
0
DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
#0
1
DMA channel is enabled
#1
SOURCE
DMA Channel Source (Slot)
0
6
read-write
TRIG
DMA Channel Trigger Enable
6
1
read-write
0
Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#0
1
Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in Periodic Trigger mode.
#1
CHCFG3
Channel Configuration register
0x6
8
read-write
n
0x0
0x0
ENBL
DMA Channel Enable
7
1
read-write
0
DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel.
#0
1
DMA channel is enabled
#1
SOURCE
DMA Channel Source (Slot)
0
6
read-write
TRIG
DMA Channel Trigger Enable
6
1
read-write
0
Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#0
1
Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in Periodic Trigger mode.
#1
FGPIOA
General Purpose Input/Output
FGPIO
0x0
0x0
0x18
registers
n
PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
FGPIOB
General Purpose Input/Output
FGPIO
0x0
0x0
0x18
registers
n
PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
FPTA
General Purpose Input/Output
FGPIO
0x0
0x0
0x18
registers
n
FGPIOA_PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
FGPIOA_PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
FGPIOA_PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
FGPIOA_PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
FGPIOA_PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
FGPIOA_PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
FPTB
General Purpose Input/Output
FGPIO
0x0
0x0
0x18
registers
n
FGPIOB_PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
FGPIOB_PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
FGPIOB_PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
FGPIOB_PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
FGPIOB_PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
FGPIOB_PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
FTFA
Flash Memory Interface
FTFA
0x0
0x0
0x14
registers
n
FTFA
5
INT_FTFA
5
FCCOB0
Flash Common Command Object Registers
0x1A
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOB1
Flash Common Command Object Registers
0x13
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOB2
Flash Common Command Object Registers
0xD
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOB3
Flash Common Command Object Registers
0x8
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOB4
Flash Common Command Object Registers
0x40
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOB5
Flash Common Command Object Registers
0x35
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOB6
Flash Common Command Object Registers
0x2B
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOB7
Flash Common Command Object Registers
0x22
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOB8
Flash Common Command Object Registers
0x76
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOB9
Flash Common Command Object Registers
0x67
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOBA
Flash Common Command Object Registers
0x59
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOBB
Flash Common Command Object Registers
0x4C
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCNFG
Flash Configuration Register
0x1
8
read-write
n
0x0
0x0
CCIE
Command Complete Interrupt Enable
7
1
read-write
0
Command complete interrupt disabled
#0
1
Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
#1
ERSAREQ
Erase All Request
5
1
read-only
0
No request or request complete
#0
1
Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state.
#1
ERSSUSP
Erase Suspend
4
1
read-write
0
No suspend requested
#0
1
Suspend the current Erase Flash Sector command execution.
#1
RDCOLLIE
Read Collision Error Interrupt Enable
6
1
read-write
0
Read collision error interrupt disabled
#0
1
Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]).
#1
RESERVED
no description available
0
3
read-only
RESERVED
no description available
3
1
read-only
FOPT
Flash Option Register
0x3
8
read-only
n
0x0
0x0
OPT
Nonvolatile Option
0
8
read-only
FPROT0
Program Flash Protection Registers
0x56
8
read-write
n
0x0
0x0
PROT
Program Flash Region Protect
0
8
read-write
0
Program flash region is protected.
#0
1
Program flash region is not protected
#1
FPROT1
Program Flash Protection Registers
0x43
8
read-write
n
0x0
0x0
PROT
Program Flash Region Protect
0
8
read-write
0
Program flash region is protected.
#0
1
Program flash region is not protected
#1
FPROT2
Program Flash Protection Registers
0x31
8
read-write
n
0x0
0x0
PROT
Program Flash Region Protect
0
8
read-write
0
Program flash region is protected.
#0
1
Program flash region is not protected
#1
FPROT3
Program Flash Protection Registers
0x20
8
read-write
n
0x0
0x0
PROT
Program Flash Region Protect
0
8
read-write
0
Program flash region is protected.
#0
1
Program flash region is not protected
#1
FSEC
Flash Security Register
0x2
8
read-only
n
0x0
0x0
FSLACC
Freescale Failure Analysis Access Code
2
2
read-only
00
Freescale factory access granted
#00
01
Freescale factory access denied
#01
10
Freescale factory access denied
#10
11
Freescale factory access granted
#11
KEYEN
Backdoor Key Security Enable
6
2
read-only
00
Backdoor key access disabled
#00
01
Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
#01
10
Backdoor key access enabled
#10
11
Backdoor key access disabled
#11
MEEN
Mass Erase Enable Bits
4
2
read-only
00
Mass erase is enabled
#00
01
Mass erase is enabled
#01
10
Mass erase is disabled
#10
11
Mass erase is enabled
#11
SEC
Flash Security
0
2
read-only
00
MCU security status is secure
#00
01
MCU security status is secure
#01
10
MCU security status is unsecure (The standard shipping condition of the flash memory module is unsecure.)
#10
11
MCU security status is secure
#11
FSTAT
Flash Status Register
0x0
8
read-write
n
0x0
0x0
ACCERR
Flash Access Error Flag
5
1
read-write
0
No access error detected
#0
1
Access error detected
#1
CCIF
Command Complete Interrupt Flag
7
1
read-write
0
Flash command in progress
#0
1
Flash command has completed
#1
FPVIOL
Flash Protection Violation Flag
4
1
read-write
0
No protection violation detected
#0
1
Protection violation detected
#1
MGSTAT0
Memory Controller Command Completion Status Flag
0
1
read-only
RDCOLERR
Flash Read Collision Error Flag
6
1
read-write
0
No collision error detected
#0
1
Collision error detected
#1
RESERVED
no description available
1
3
read-only
FTFA_FlashConfig
Flash configuration field
FTFA_FlashConfig
0x0
0x0
0xE
registers
n
BACKKEY0
Backdoor Comparison Key 0.
0x3
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY1
Backdoor Comparison Key 1.
0x2
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY2
Backdoor Comparison Key 2.
0x1
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY3
Backdoor Comparison Key 3.
0x0
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY4
Backdoor Comparison Key 4.
0x7
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY5
Backdoor Comparison Key 5.
0x6
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY6
Backdoor Comparison Key 6.
0x5
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY7
Backdoor Comparison Key 7.
0x4
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
FOPT
Non-volatile Flash Option Register
0xD
8
read-only
n
0x0
0x0
FAST_INIT
no description available
5
1
read-only
LPBOOT0
no description available
0
1
read-only
LPBOOT1
no description available
4
1
read-only
NMI_DIS
no description available
2
1
read-only
RESERVED
no description available
6
1
read-only
RESERVED
no description available
6
1
read-only
RESERVED
no description available
7
1
read-only
RESET_PIN_CFG
no description available
3
1
read-only
FPROT0
Non-volatile P-Flash Protection 0 - High Register
0xB
8
read-only
n
0x0
0x0
PROT
P-Flash Region Protect
0
8
read-only
FPROT1
Non-volatile P-Flash Protection 0 - Low Register
0xA
8
read-only
n
0x0
0x0
PROT
P-Flash Region Protect
0
8
read-only
FPROT2
Non-volatile P-Flash Protection 1 - High Register
0x9
8
read-only
n
0x0
0x0
PROT
P-Flash Region Protect
0
8
read-only
FPROT3
Non-volatile P-Flash Protection 1 - Low Register
0x8
8
read-only
n
0x0
0x0
PROT
P-Flash Region Protect
0
8
read-only
FSEC
Non-volatile Flash Security Register
0xC
8
read-only
n
0x0
0x0
FSLACC
Freescale Failure Analysis Access Code
2
2
read-only
KEYEN
Backdoor Key Security Enable
6
2
read-only
MEEN
no description available
4
2
read-only
SEC
Flash Security
0
2
read-only
NV_BACKKEY0
Backdoor Comparison Key 0.
0x3
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY1
Backdoor Comparison Key 1.
0x2
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY2
Backdoor Comparison Key 2.
0x1
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY3
Backdoor Comparison Key 3.
0x0
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY4
Backdoor Comparison Key 4.
0x7
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY5
Backdoor Comparison Key 5.
0x6
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY6
Backdoor Comparison Key 6.
0x5
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY7
Backdoor Comparison Key 7.
0x4
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_FOPT
Non-volatile Flash Option Register
0xD
8
read-only
n
0x0
0x0
FAST_INIT
no description available
5
1
read-only
00
Slower initialization
#00
01
Fast Initialization
#01
LPBOOT0
no description available
0
1
read-only
00
Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1.
#00
01
Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1.
#01
LPBOOT1
no description available
4
1
read-only
00
Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1.
#00
01
Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1.
#01
NMI_DIS
no description available
2
1
read-only
00
NMI interrupts are always blocked
#00
01
NMI_b pin/interrupts reset default to enabled
#01
RESERVED
no description available
1
1
read-only
RESERVED
no description available
6
1
read-only
RESERVED
no description available
7
1
read-only
RESET_PIN_CFG
no description available
3
1
read-only
00
RESET pin is disabled following a POR and cannot be enabled as reset function
#00
01
RESET_b pin is dedicated
#01
NV_FPROT0
Non-volatile P-Flash Protection 0 - High Register
0xB
8
read-only
n
0x0
0x0
PROT
P-Flash Region Protect
0
8
read-only
NV_FPROT1
Non-volatile P-Flash Protection 0 - Low Register
0xA
8
read-only
n
0x0
0x0
PROT
P-Flash Region Protect
0
8
read-only
NV_FPROT2
Non-volatile P-Flash Protection 1 - High Register
0x9
8
read-only
n
0x0
0x0
PROT
P-Flash Region Protect
0
8
read-only
NV_FPROT3
Non-volatile P-Flash Protection 1 - Low Register
0x8
8
read-only
n
0x0
0x0
PROT
P-Flash Region Protect
0
8
read-only
NV_FSEC
Non-volatile Flash Security Register
0xC
8
read-only
n
0x0
0x0
FSLACC
Freescale Failure Analysis Access Code
2
2
read-only
10
Freescale factory access denied
#10
11
Freescale factory access granted
#11
KEYEN
Backdoor Key Security Enable
6
2
read-only
10
Backdoor key access enabled
#10
11
Backdoor key access disabled
#11
MEEN
no description available
4
2
read-only
10
Mass erase is disabled
#10
11
Mass erase is enabled
#11
SEC
Flash Security
0
2
read-only
10
MCU security status is unsecure
#10
11
MCU security status is secure
#11
GPIOA
General Purpose Input/Output
GPIO
0x0
0x0
0x18
registers
n
PORTA
30
PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
GPIOB
General Purpose Input/Output
GPIO
0x0
0x0
0x18
registers
n
PORTB
31
PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
I2C0
Inter-Integrated Circuit
I2C0
0x0
0x0
0xC
registers
n
I2C0
8
INT_I2C0
8
A1
I2C Address Register 1
0x0
8
read-write
n
0x0
0x0
AD
Address
1
7
read-write
RESERVED
no description available
0
1
read-only
A2
I2C Address Register 2
0x9
8
read-write
n
0x0
0x0
RESERVED
no description available
0
1
read-only
SAD
SMBus Address
1
7
read-write
C1
I2C Control Register 1
0x2
8
read-write
n
0x0
0x0
DMAEN
DMA Enable
0
1
read-write
0
All DMA signalling disabled.
#0
1
DMA transfer is enabled and the following conditions trigger the DMA request: While FACK = 0, a data byte is received, either address or data is transmitted. (ACK/NACK automatic) While FACK = 0, the first byte received matches the A1 register or is general call address. If any address matching occurs, IAAS and TCF are set. If the direction of transfer is known from master to slave, then it is not required to check the SRW. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.
#1
IICEN
I2C Enable
7
1
read-write
0
Disabled
#0
1
Enabled
#1
IICIE
I2C Interrupt Enable
6
1
read-write
0
Disabled
#0
1
Enabled
#1
MST
Master Mode Select
5
1
read-write
0
Slave mode
#0
1
Master mode
#1
RSTA
Repeat START
2
1
write-only
TX
Transmit Mode Select
4
1
read-write
0
Receive
#0
1
Transmit
#1
TXAK
Transmit Acknowledge Enable
3
1
read-write
0
An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).
#0
1
No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).
#1
WUEN
Wakeup Enable
1
1
read-write
0
Normal operation. No interrupt generated when address matching in low power mode.
#0
1
Enables the wakeup function in low power mode.
#1
C2
I2C Control Register 2
0x5
8
read-write
n
0x0
0x0
AD
Slave Address
0
3
read-write
ADEXT
Address Extension
6
1
read-write
0
7-bit address scheme
#0
1
10-bit address scheme
#1
GCAEN
General Call Address Enable
7
1
read-write
0
Disabled
#0
1
Enabled
#1
HDRS
High Drive Select
5
1
read-write
0
Normal drive mode
#0
1
High drive mode
#1
RMEN
Range Address Matching Enable
3
1
read-write
0
Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers.
#0
1
Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
#1
SBRC
Slave Baud Rate Control
4
1
read-write
0
The slave baud rate follows the master baud rate and clock stretching may occur
#0
1
Slave baud rate is independent of the master baud rate
#1
D
I2C Data I/O register
0x4
8
read-write
n
0x0
0x0
DATA
Data
0
8
read-write
F
I2C Frequency Divider register
0x1
8
read-write
n
0x0
0x0
ICR
ClockRate
0
6
read-write
MULT
no description available
6
2
read-write
00
mul = 1
#00
01
mul = 2
#01
10
mul = 4
#10
11
Reserved
#11
FLT
I2C Programmable Input Glitch Filter register
0x6
8
read-write
n
0x0
0x0
FLT
I2C Programmable Filter Factor
0
5
read-write
0
No filter/bypass
#0
SHEN
Stop Hold Enable
7
1
read-write
0
Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
#0
1
Stop holdoff is enabled.
#1
STOPF
I2C Bus Stop Detect Flag
6
1
read-write
0
No stop happens on I2C bus
#0
1
Stop detected on I2C bus
#1
STOPIE
I2C Bus Stop Interrupt Enable
5
1
read-write
0
Stop detection interrupt is disabled
#0
1
Stop detection interrupt is enabled
#1
RA
I2C Range Address register
0x7
8
read-write
n
0x0
0x0
RAD
Range Slave Address
1
7
read-write
RESERVED
no description available
0
1
read-only
S
I2C Status register
0x3
8
read-write
n
0x0
0x0
ARBL
Arbitration Lost
4
1
read-write
0
Standard bus operation.
#0
1
Loss of arbitration.
#1
BUSY
Bus Busy
5
1
read-only
0
Bus is idle
#0
1
Bus is busy
#1
IAAS
Addressed As A Slave
6
1
read-write
0
Not addressed
#0
1
Addressed as a slave
#1
IICIF
Interrupt Flag
1
1
read-write
0
No interrupt pending
#0
1
Interrupt pending
#1
RAM
Range Address Match
3
1
read-write
0
Not addressed
#0
1
Addressed as a slave
#1
RXAK
Receive Acknowledge
0
1
read-only
0
Acknowledge signal was received after the completion of one byte of data transmission on the bus
#0
1
No acknowledge signal detected
#1
SRW
Slave Read/Write
2
1
read-only
0
Slave receive, master writing to slave
#0
1
Slave transmit, master reading from slave
#1
TCF
Transfer Complete Flag
7
1
read-only
0
Transfer in progress
#0
1
Transfer complete
#1
SLTH
I2C SCL Low Timeout Register High
0xA
8
read-write
n
0x0
0x0
SSLT
no description available
0
8
read-write
SLTL
I2C SCL Low Timeout Register Low
0xB
8
read-write
n
0x0
0x0
SSLT
no description available
0
8
read-write
SMB
I2C SMBus Control and Status register
0x8
8
read-write
n
0x0
0x0
ALERTEN
SMBus Alert Response Address Enable
6
1
read-write
0
SMBus alert response address matching is disabled
#0
1
SMBus alert response address matching is enabled
#1
FACK
Fast NACK/ACK Enable
7
1
read-write
0
An ACK or NACK is sent on the following receiving data byte
#0
1
Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
#1
SHTF1
SCL High Timeout Flag 1
2
1
read-only
0
No SCL high and SDA high timeout occurs
#0
1
SCL high and SDA high timeout occurs
#1
SHTF2
SCL High Timeout Flag 2
1
1
read-write
0
No SCL high and SDA low timeout occurs
#0
1
SCL high and SDA low timeout occurs
#1
SHTF2IE
SHTF2 Interrupt Enable
0
1
read-write
0
SHTF2 interrupt is disabled
#0
1
SHTF2 interrupt is enabled
#1
SIICAEN
Second I2C Address Enable
5
1
read-write
0
I2C address register 2 matching is disabled
#0
1
I2C address register 2 matching is enabled
#1
SLTF
SCL Low Timeout Flag
3
1
read-write
0
No low timeout occurs
#0
1
Low timeout occurs
#1
TCKSEL
Timeout Counter Clock Select
4
1
read-write
0
Timeout counter counts at the frequency of the bus clock / 64
#0
1
Timeout counter counts at the frequency of the bus clock
#1
LLWU
Low leakage wakeup unit
LLWU
0x0
0x0
0x7
registers
n
LLW
7
INT_LLW
7
F1
LLWU Flag 1 register
0x3
8
read-write
n
0x0
0x0
WUF0
Wakeup Flag For LLWU_P0
0
1
read-write
0
LLWU_P0 input was not a wakeup source
#0
1
LLWU_P0 input was a wakeup source
#1
WUF1
Wakeup Flag For LLWU_P1
1
1
read-write
0
LLWU_P1 input was not a wakeup source
#0
1
LLWU_P1 input was a wakeup source
#1
WUF2
Wakeup Flag For LLWU_P2
2
1
read-write
0
LLWU_P2 input was not a wakeup source
#0
1
LLWU_P2 input was a wakeup source
#1
WUF3
Wakeup Flag For LLWU_P3
3
1
read-write
0
LLWU_P3 input was not a wakeup source
#0
1
LLWU_P3 input was a wakeup source
#1
WUF4
Wakeup Flag For LLWU_P4
4
1
read-write
0
LLWU_P4 input was not a wakeup source
#0
1
LLWU_P4 input was a wakeup source
#1
WUF5
Wakeup Flag For LLWU_P5
5
1
read-write
0
LLWU_P5 input was not a wakeup source
#0
1
LLWU_P5 input was a wakeup source
#1
WUF6
Wakeup Flag For LLWU_P6
6
1
read-write
0
LLWU_P6 input was not a wakeup source
#0
1
LLWU_P6 input was a wakeup source
#1
WUF7
Wakeup Flag For LLWU_P7
7
1
read-write
0
LLWU_P7 input was not a wakeup source
#0
1
LLWU_P7 input was a wakeup source
#1
F3
LLWU Flag 3 register
0x4
8
read-only
n
0x0
0x0
MWUF0
Wakeup flag For module 0
0
1
read-only
0
Module 0 input was not a wakeup source
#0
1
Module 0 input was a wakeup source
#1
MWUF1
Wakeup flag For module 1
1
1
read-only
0
Module 1 input was not a wakeup source
#0
1
Module 1 input was a wakeup source
#1
MWUF2
Wakeup flag For module 2
2
1
read-only
0
Module 2 input was not a wakeup source
#0
1
Module 2 input was a wakeup source
#1
MWUF3
Wakeup flag For module 3
3
1
read-only
0
Module 3 input was not a wakeup source
#0
1
Module 3 input was a wakeup source
#1
MWUF4
Wakeup flag For module 4
4
1
read-only
0
Module 4 input was not a wakeup source
#0
1
Module 4 input was a wakeup source
#1
MWUF5
Wakeup flag For module 5
5
1
read-only
0
Module 5 input was not a wakeup source
#0
1
Module 5 input was a wakeup source
#1
MWUF6
Wakeup flag For module 6
6
1
read-only
0
Module 6 input was not a wakeup source
#0
1
Module 6 input was a wakeup source
#1
MWUF7
Wakeup flag For module 7
7
1
read-only
0
Module 7 input was not a wakeup source
#0
1
Module 7 input was a wakeup source
#1
FILT1
LLWU Pin Filter 1 register
0x5
8
read-write
n
0x0
0x0
FILTE
Digital Filter On External Pin
5
2
read-write
00
Filter disabled
#00
01
Filter posedge detect enabled
#01
10
Filter negedge detect enabled
#10
11
Filter any edge detect enabled
#11
FILTF
Filter Detect Flag
7
1
read-write
0
Pin Filter 1 was not a wakeup source
#0
1
Pin Filter 1 was a wakeup source
#1
FILTSEL
Filter Pin Select
0
4
read-write
0000
Select LLWU_P0 for filter
#0000
1111
Select LLWU_P15 for filter
#1111
RESERVED
no description available
4
1
read-only
FILT2
LLWU Pin Filter 2 register
0x6
8
read-write
n
0x0
0x0
FILTE
Digital Filter On External Pin
5
2
read-write
00
Filter disabled
#00
01
Filter posedge detect enabled
#01
10
Filter negedge detect enabled
#10
11
Filter any edge detect enabled
#11
FILTF
Filter Detect Flag
7
1
read-write
0
Pin Filter 2 was not a wakeup source
#0
1
Pin Filter 2 was a wakeup source
#1
FILTSEL
Filter Pin Select
0
4
read-write
0000
Select LLWU_P0 for filter
#0000
1111
Select LLWU_P15 for filter
#1111
RESERVED
no description available
4
1
read-only
ME
LLWU Module Enable register
0x2
8
read-write
n
0x0
0x0
WUME0
Wakeup Module Enable For Module 0
0
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME1
Wakeup Module Enable for Module 1
1
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME2
Wakeup Module Enable For Module 2
2
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME3
Wakeup Module Enable For Module 3
3
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME4
Wakeup Module Enable For Module 4
4
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME5
Wakeup Module Enable For Module 5
5
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME6
Wakeup Module Enable For Module 6
6
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME7
Wakeup Module Enable For Module 7
7
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
PE1
LLWU Pin Enable 1 register
0x0
8
read-write
n
0x0
0x0
WUPE0
Wakeup Pin Enable For LLWU_P0
0
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE1
Wakeup Pin Enable For LLWU_P1
2
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE2
Wakeup Pin Enable For LLWU_P2
4
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE3
Wakeup Pin Enable For LLWU_P3
6
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
PE2
LLWU Pin Enable 2 register
0x1
8
read-write
n
0x0
0x0
WUPE4
Wakeup Pin Enable For LLWU_P4
0
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE5
Wakeup Pin Enable For LLWU_P5
2
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE6
Wakeup Pin Enable For LLWU_P6
4
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE7
Wakeup Pin Enable For LLWU_P7
6
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
LPTMR0
Low Power Timer
LPTMR0
0x0
0x0
0x10
registers
n
LPTMR0
28
INT_LPTimer
28
CMR
Low Power Timer Compare Register
0x8
32
read-write
n
0x0
0x0
COMPARE
Compare Value
0
16
read-write
RESERVED
no description available
16
16
read-only
CNR
Low Power Timer Counter Register
0xC
32
read-only
n
0x0
0x0
COUNTER
Counter Value
0
16
read-only
RESERVED
no description available
16
16
read-only
CSR
Low Power Timer Control Status Register
0x0
32
read-write
n
0x0
0x0
RESERVED
no description available
8
24
read-only
TCF
Timer Compare Flag
7
1
read-write
0
The value of CNR is not equal to CMR and increments.
#0
1
The value of CNR is equal to CMR and increments.
#1
TEN
Timer Enable
0
1
read-write
0
LPTMR is disabled and internal logic is reset.
#0
1
LPTMR is enabled.
#1
TFC
Timer Free-Running Counter
2
1
read-write
0
CNR is reset whenever TCF is set.
#0
1
CNR is reset on overflow.
#1
TIE
Timer Interrupt Enable
6
1
read-write
0
Timer interrupt disabled.
#0
1
Timer interrupt enabled.
#1
TMS
Timer Mode Select
1
1
read-write
0
Time Counter mode.
#0
1
Pulse Counter mode.
#1
TPP
Timer Pin Polarity
3
1
read-write
0
Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.
#0
1
Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.
#1
TPS
Timer Pin Select
4
2
read-write
00
Pulse counter input 0 is selected.
#00
01
Pulse counter input 1 is selected.
#01
10
Pulse counter input 2 is selected.
#10
11
Pulse counter input 3 is selected.
#11
PSR
Low Power Timer Prescale Register
0x4
32
read-write
n
0x0
0x0
PBYP
Prescaler Bypass
2
1
read-write
0
Prescaler/glitch filter is enabled.
#0
1
Prescaler/glitch filter is bypassed.
#1
PCS
Prescaler Clock Select
0
2
read-write
00
Prescaler/glitch filter clock 0 selected.
#00
01
Prescaler/glitch filter clock 1 selected.
#01
10
Prescaler/glitch filter clock 2 selected.
#10
11
Prescaler/glitch filter clock 3 selected.
#11
PRESCALE
Prescale Value
3
4
read-write
0000
Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.
#0000
0001
Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.
#0001
0010
Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.
#0010
0011
Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.
#0011
0100
Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.
#0100
0101
Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.
#0101
0110
Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.
#0110
0111
Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.
#0111
1000
Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.
#1000
1001
Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.
#1001
1010
Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.
#1010
1011
Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.
#1011
1100
Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.
#1100
1101
Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.
#1101
1110
Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.
#1110
1111
Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.
#1111
RESERVED
no description available
7
25
read-only
MCG
Multipurpose Clock Generator module
MCG
0x0
0x0
0xC
registers
n
MCG
27
ATCVH
MCG Auto Trim Compare Value High Register
0xA
8
read-write
n
0x0
0x0
ATCVH
ATM Compare Value High
0
8
read-write
ATCVL
MCG Auto Trim Compare Value Low Register
0xB
8
read-write
n
0x0
0x0
ATCVL
ATM Compare Value Low
0
8
read-write
C1
MCG Control 1 Register
0x0
8
read-write
n
0x0
0x0
CLKS
Clock Source Select
6
2
read-write
00
Encoding 0 - Output of FLL is selected.
#00
01
Encoding 1 - Internal reference clock is selected.
#01
10
Encoding 2 - External reference clock is selected.
#10
11
Encoding 3 - Reserved.
#11
FRDIV
FLL External Reference Divider
3
3
read-write
000
If RANGE 0 = 0 , Divide Factor is 1; for all other RANGE 0 values, Divide Factor is 32.
#000
001
If RANGE 0 = 0 , Divide Factor is 2; for all other RANGE 0 values, Divide Factor is 64.
#001
010
If RANGE 0 = 0 , Divide Factor is 4; for all other RANGE 0 values, Divide Factor is 128.
#010
011
If RANGE 0 = 0 , Divide Factor is 8; for all other RANGE 0 values, Divide Factor is 256.
#011
100
If RANGE 0 = 0 , Divide Factor is 16; for all other RANGE 0 values, Divide Factor is 512.
#100
101
If RANGE 0 = 0 , Divide Factor is 32; for all other RANGE 0 values, Divide Factor is 1024.
#101
110
If RANGE 0 = 0 , Divide Factor is 64; for all other RANGE 0 values, Divide Factor is 1280 .
#110
111
If RANGE 0 = 0 , Divide Factor is 128; for all other RANGE 0 values, Divide Factor is 1536 .
#111
IRCLKEN
Internal Reference Clock Enable
1
1
read-write
0
MCGIRCLK inactive.
#0
1
MCGIRCLK active.
#1
IREFS
Internal Reference Select
2
1
read-write
0
External reference clock is selected.
#0
1
The slow internal reference clock is selected.
#1
IREFSTEN
Internal Reference Stop Enable
0
1
read-write
0
Internal reference clock is disabled in Stop mode.
#0
1
Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
#1
C2
MCG Control 2 Register
0x1
8
read-write
n
0x0
0x0
EREFS0
External Reference Select
2
1
read-write
0
External reference clock requested.
#0
1
Oscillator requested.
#1
HGO0
High Gain Oscillator Select
3
1
read-write
0
Configure crystal oscillator for low-power operation.
#0
1
Configure crystal oscillator for high-gain operation.
#1
IRCS
Internal Reference Clock Select
0
1
read-write
0
Slow internal reference clock selected.
#0
1
Fast internal reference clock selected.
#1
LOCRE0
Loss of Clock Reset Enable
7
1
read-write
0
Interrupt request is generated on a loss of OSC0 external reference clock.
#0
1
Generate a reset request on a loss of OSC0 external reference clock.
#1
LP
Low Power Select
1
1
read-write
0
FLL is not disabled in bypass modes.
#0
1
FLL is disabled in bypass modes (lower power)
#1
RANGE0
Frequency Range Select
4
2
read-write
00
Encoding 0 - Low frequency range selected for the crystal oscillator .
#00
01
Encoding 1 - High frequency range selected for the crystal oscillator .
#01
RESERVED
no description available
6
1
read-only
C3
MCG Control 3 Register
0x2
8
read-write
n
0x0
0x0
SCTRIM
Slow Internal Reference Clock Trim Setting
0
8
read-write
C4
MCG Control 4 Register
0x3
8
read-write
n
0x0
0x0
DMX32
DCO Maximum Frequency with 32.768 kHz Reference
7
1
read-write
0
DCO has a default range of 25%.
#0
1
DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
#1
DRST_DRS
DCO Range Select
5
2
read-write
00
Encoding 0 - Low range (reset default).
#00
01
Encoding 1 - Mid range.
#01
10
Encoding 2 - Mid-high range.
#10
11
Encoding 3 - High range.
#11
FCTRIM
Fast Internal Reference Clock Trim Setting
1
4
read-write
SCFTRIM
Slow Internal Reference Clock Fine Trim
0
1
read-write
C5
MCG Control 5 Register
0x4
8
read-only
n
0x0
0x0
RESERVED
Reserved
0
8
read-only
C6
MCG Control 6 Register
0x5
8
read-write
n
0x0
0x0
CME
Clock Monitor Enable
5
1
read-write
0
External clock monitor is disabled.
#0
1
Generate a reset request on loss of external clock.
#1
RESERVED
Reserved
0
5
read-only
RESERVED
Reserved
6
2
read-only
S
MCG Status Register
0x6
8
read-only
n
0x0
0x0
CLKST
Clock Mode Status
2
2
read-only
00
Encoding 0 - Output of the FLL is selected (reset default).
#00
01
Encoding 1 - Internal reference clock is selected.
#01
10
Encoding 2 - External reference clock is selected.
#10
11
Reserved.
#11
IRCST
Internal Reference Clock Status
0
1
read-only
0
Source of internal reference clock is the slow clock (32 kHz IRC).
#0
1
Source of internal reference clock is the fast clock (4 MHz IRC).
#1
IREFST
Internal Reference Status
4
1
read-only
0
Source of FLL reference clock is the external reference clock.
#0
1
Source of FLL reference clock is the internal reference clock.
#1
OSCINIT0
OSC Initialization
1
1
read-only
RESERVED
Reserved
5
3
read-only
SC
MCG Status and Control Register
0x8
8
read-write
n
0x0
0x0
ATME
Automatic Trim Machine Enable
7
1
read-write
0
Auto Trim Machine disabled.
#0
1
Auto Trim Machine enabled.
#1
ATMF
Automatic Trim Machine Fail Flag
5
1
read-only
0
Automatic Trim Machine completed normally.
#0
1
Automatic Trim Machine failed.
#1
ATMS
Automatic Trim Machine Select
6
1
read-write
0
32 kHz Internal Reference Clock selected.
#0
1
4 MHz Internal Reference Clock selected.
#1
FCRDIV
Fast Clock Internal Reference Divider
1
3
read-write
000
Divide Factor is 1
#000
001
Divide Factor is 2.
#001
010
Divide Factor is 4.
#010
011
Divide Factor is 8.
#011
100
Divide Factor is 16
#100
101
Divide Factor is 32
#101
110
Divide Factor is 64
#110
111
Divide Factor is 128.
#111
FLTPRSRV
FLL Filter Preserve Enable
4
1
read-write
0
FLL filter and FLL frequency will reset on changes to currect clock mode.
#0
1
Fll filter and FLL frequency retain their previous values during new clock mode change.
#1
LOCS0
OSC0 Loss of Clock Status
0
1
read-only
0
Loss of OSC0 has not occurred.
#0
1
Loss of OSC0 has occurred.
#1
MCM
Core Platform Miscellaneous Control Module
MCM
0x0
0x8
0x3C
registers
n
CPO
Compute Operation Control Register
0x40
32
read-write
n
0x0
0x0
CPOACK
Compute Operation acknowledge
1
1
read-only
0
Compute operation entry has not completed or compute operation exit has completed.
#0
1
Compute operation entry has completed or compute operation exit has not completed.
#1
CPOREQ
Compute Operation request
0
1
read-write
0
Request is cleared.
#0
1
Request Compute Operation.
#1
CPOWOI
Compute Operation wakeup on interrupt
2
1
read-write
0
No effect.
#0
1
When set, the CPOREQ is cleared on any interrupt or exception vector fetch.
#1
RESERVED
no description available
3
29
read-only
PLACR
Platform Control Register
0xC
32
read-write
n
0x0
0x0
ARB
Arbitration select
9
1
read-write
0
Fixed-priority arbitration for the crossbar masters
#0
1
Round-robin arbitration for the crossbar masters
#1
CFCC
Clear Flash Controller Cache
10
1
write-only
DFCC
Disable Flash Controller Cache
13
1
read-write
0
Enable flash controller cache.
#0
1
Disable flash controller cache.
#1
DFCDA
Disable Flash Controller Data Caching
11
1
read-write
0
Enable flash controller data caching
#0
1
Disable flash controller data caching.
#1
DFCIC
Disable Flash Controller Instruction Caching
12
1
read-write
0
Enable flash controller instruction caching.
#0
1
Disable flash controller instruction caching.
#1
DFCS
Disable Flash Controller Speculation
15
1
read-write
0
Enable flash controller speculation.
#0
1
Disable flash controller speculation.
#1
EFDS
Enable Flash Data Speculation
14
1
read-write
0
Disable flash data speculation.
#0
1
Enable flash data speculation.
#1
ESFC
Enable Stalling Flash Controller
16
1
read-write
0
Disable stalling flash controller when flash is busy.
#0
1
Enable stalling flash controller when flash is busy.
#1
RESERVED
no description available
0
9
read-only
RESERVED
no description available
17
15
read-only
PLAMC
Crossbar Switch (AXBS) Master Configuration
0xA
16
read-only
n
0x0
0x0
AMC
Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
0
8
read-only
0
A bus master connection to AXBS input port n is absent
#0
1
A bus master connection to AXBS input port n is present
#1
RESERVED
no description available
8
8
read-only
PLASC
Crossbar Switch (AXBS) Slave Configuration
0x8
16
read-only
n
0x0
0x0
ASC
Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.
0
8
read-only
0
A bus slave connection to AXBS input port n is absent
#0
1
A bus slave connection to AXBS input port n is present
#1
RESERVED
no description available
8
8
read-only
MTB
Micro Trace Buffer
MTB
0x0
0x0
0x1000
registers
n
AUTHSTAT
Authentication Status Register
0xFB8
32
read-only
n
0x0
0x0
BIT0
no description available
0
1
read-only
BIT1
no description available
1
1
read-only
BIT2
no description available
2
1
read-only
BIT3
no description available
3
1
read-only
RESERVED
no description available
4
28
read-only
BASE
MTB Base Register
0xC
32
read-only
n
0x0
0x0
BASEADDR
no description available
0
32
read-only
COMPID0
Component ID Register
0x1FE0
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID1
Component ID Register
0x2FD4
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID2
Component ID Register
0x3FCC
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID3
Component ID Register
0x4FC8
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
DEVICEARCH
Device Architecture Register
0xFBC
32
read-only
n
0x0
0x0
DEVICEARCH
no description available
0
32
read-only
DEVICECFG
Device Configuration Register
0xFC8
32
read-only
n
0x0
0x0
DEVICECFG
no description available
0
32
read-only
DEVICETYPID
Device Type Identifier Register
0xFCC
32
read-only
n
0x0
0x0
DEVICETYPID
no description available
0
32
read-only
FLOW
MTB Flow Register
0x8
32
read-write
n
0x0
0x0
AUTOHALT
no description available
1
1
read-write
AUTOSTOP
no description available
0
1
read-write
RESERVED
no description available
2
1
read-only
WATERMARK
WATERMARK value
3
29
read-write
LOCKACCESS
Lock Access Register
0xFB0
32
read-only
n
0x0
0x0
LOCKACCESS
no description available
0
32
read-only
LOCKSTAT
Lock Status Register
0xFB4
32
read-only
n
0x0
0x0
LOCKSTAT
no description available
0
32
read-only
MASTER
MTB Master Register
0x4
32
read-write
n
0x0
0x0
EN
Main trace enable bit
31
1
read-write
HALTREQ
Halt request bit
9
1
read-write
MASK
Mask
0
5
read-write
RAMPRIV
RAM privilege bit
8
1
read-write
RESERVED
no description available
10
21
read-only
SFRWPRIV
Special Function Register Write Privilege bit
7
1
read-write
TSTARTEN
Trace start input enable
5
1
read-write
TSTOPEN
Trace stop input enable
6
1
read-write
MODECTRL
Integration Mode Control Register
0xF00
32
read-only
n
0x0
0x0
MODECTRL
no description available
0
32
read-only
PERIPHID0
Peripheral ID Register
0x5F08
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID1
Peripheral ID Register
0x6EEC
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID2
Peripheral ID Register
0x7ED4
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID3
Peripheral ID Register
0x8EC0
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID4
Peripheral ID Register
0x1FA0
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID5
Peripheral ID Register
0x2F74
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID6
Peripheral ID Register
0x3F4C
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID7
Peripheral ID Register
0x4F28
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
POSITION
MTB Position Register
0x0
32
read-write
n
0x0
0x0
POINTER
Trace Packet Address Pointer
3
29
read-write
RESERVED
no description available
0
2
read-only
WRAP
no description available
2
1
read-write
TAGCLEAR
Claim TAG Clear Register
0xFA4
32
read-only
n
0x0
0x0
TAGCLEAR
no description available
0
32
read-only
TAGSET
Claim TAG Set Register
0xFA0
32
read-only
n
0x0
0x0
TAGSET
no description available
0
32
read-only
MTBDWT
MTB data watchpoint and trace
MTBDWT
0x0
0x0
0x1000
registers
n
COMP0
MTB_DWT Comparator Register
0x40
32
read-write
n
0x0
0x0
COMP
Reference value for comparison
0
32
read-write
COMP1
MTB_DWT Comparator Register
0x70
32
read-write
n
0x0
0x0
COMP
Reference value for comparison
0
32
read-write
COMPID0
Component ID Register
0x1FE0
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID1
Component ID Register
0x2FD4
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID2
Component ID Register
0x3FCC
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID3
Component ID Register
0x4FC8
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
CTRL
MTB DWT Control Register
0x0
32
read-only
n
0x0
0x0
DWTCFGCTRL
DWT configuration controls
0
28
read-only
NUMCMP
Number of comparators
28
4
read-only
DEVICECFG
Device Configuration Register
0xFC8
32
read-only
n
0x0
0x0
DEVICECFG
no description available
0
32
read-only
DEVICETYPID
Device Type Identifier Register
0xFCC
32
read-only
n
0x0
0x0
DEVICETYPID
no description available
0
32
read-only
FCT0
MTB_DWT Comparator Function Register 0
0x28
32
read-write
n
0x0
0x0
DATAVADDR0
Data Value Address 0
12
4
read-write
DATAVMATCH
Data Value Match
8
1
read-write
0
Perform address comparison.
#0
1
Perform data value comparison.
#1
DATAVSIZE
Data Value Size
10
2
read-write
00
Byte.
#00
01
Halfword.
#01
10
Word.
#10
11
Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.
#11
FUNCTION
Function
0
4
read-write
0000
Disabled.
#0000
0100
Instruction fetch.
#0100
0101
Data operand read.
#0101
0110
Data operand write.
#0110
0111
Data operand (read + write).
#0111
MATCHED
Comparator match
24
1
read-only
0
No match.
#0
1
Match occurred.
#1
RESERVED
no description available
4
4
read-only
RESERVED
no description available
9
1
read-only
RESERVED
no description available
16
4
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
FCT1
MTB_DWT Comparator Function Register 1
0x38
32
read-write
n
0x0
0x0
FUNCTION
Function
0
4
read-write
0000
Disabled.
#0000
0100
Instruction fetch.
#0100
0101
Data operand read.
#0101
0110
Data operand write.
#0110
0111
Data operand (read + write).
#0111
MATCHED
Comparator match
24
1
read-only
0
No match.
#0
1
Match occurred.
#1
RESERVED
no description available
4
20
read-only
RESERVED
no description available
25
7
read-only
MASK0
MTB_DWT Comparator Mask Register
0x48
32
read-write
n
0x0
0x0
MASK
MASK
0
5
read-write
RESERVED
no description available
5
27
read-only
MASK1
MTB_DWT Comparator Mask Register
0x7C
32
read-write
n
0x0
0x0
MASK
MASK
0
5
read-write
RESERVED
no description available
5
27
read-only
PERIPHID0
Peripheral ID Register
0x5F08
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID1
Peripheral ID Register
0x6EEC
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID2
Peripheral ID Register
0x7ED4
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID3
Peripheral ID Register
0x8EC0
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID4
Peripheral ID Register
0x1FA0
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID5
Peripheral ID Register
0x2F74
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID6
Peripheral ID Register
0x3F4C
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID7
Peripheral ID Register
0x4F28
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
TBCTRL
MTB_DWT Trace Buffer Control Register
0x200
32
read-write
n
0x0
0x0
ACOMP0
Action based on Comparator 0 match
0
1
read-write
0
Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED].
#0
1
Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED].
#1
ACOMP1
Action based on Comparator 1 match
1
1
read-write
0
Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED].
#0
1
Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED].
#1
NUMCOMP
Number of Comparators
28
4
read-only
RESERVED
no description available
2
26
read-only
NVIC
Nested Vectored Interrupt Controller
NVIC
0x0
0x0
0x320
registers
n
ICER
Interrupt Clear Enable Register
0x80
32
read-write
n
0x0
0x0
CLRENA0
no description available
0
1
read-write
0
write: no effect; read: DMA channel 0 transfer complete interrupt disabled
#0
1
write: disable DMA channel 0 transfer complete interrupt; read: DMA channel 0 transfer complete interrupt enabled
#1
CLRENA1
no description available
1
1
read-write
0
write: no effect; read: DMA channel 1 transfer complete interrupt disabled
#0
1
write: disable DMA channel 1 transfer complete interrupt; read: DMA channel 1 transfer complete interrupt enabled
#1
CLRENA10
no description available
10
1
read-write
0
write: no effect; read: Serial Peripheral Interface 0 interrupt disabled
#0
1
write: disable Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt enabled
#1
CLRENA11
no description available
11
1
read-write
0
write: no effect; read: Reserved iv 27 interrupt disabled
#0
1
write: disable Reserved iv 27 interrupt; read: Reserved iv 27 interrupt enabled
#1
CLRENA12
no description available
12
1
read-write
0
write: no effect; read: UART0 status and error interrupt disabled
#0
1
write: disable UART0 status and error interrupt; read: UART0 status and error interrupt enabled
#1
CLRENA13
no description available
13
1
read-write
0
write: no effect; read: Reserved iv 29 interrupt disabled
#0
1
write: disable Reserved iv 29 interrupt; read: Reserved iv 29 interrupt enabled
#1
CLRENA14
no description available
14
1
read-write
0
write: no effect; read: Reserved iv 30 interrupt disabled
#0
1
write: disable Reserved iv 30 interrupt; read: Reserved iv 30 interrupt enabled
#1
CLRENA15
no description available
15
1
read-write
0
write: no effect; read: Analog-to-Digital Converter 0 interrupt disabled
#0
1
write: disable Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt enabled
#1
CLRENA16
no description available
16
1
read-write
0
write: no effect; read: Comparator 0 interrupt disabled
#0
1
write: disable Comparator 0 interrupt; read: Comparator 0 interrupt enabled
#1
CLRENA17
no description available
17
1
read-write
0
write: no effect; read: Timer/PWM module 0 interrupt disabled
#0
1
write: disable Timer/PWM module 0 interrupt; read: Timer/PWM module 0 interrupt enabled
#1
CLRENA18
no description available
18
1
read-write
0
write: no effect; read: Timer/PWM module 1 interrupt disabled
#0
1
write: disable Timer/PWM module 1 interrupt; read: Timer/PWM module 1 interrupt enabled
#1
CLRENA19
no description available
19
1
read-write
0
write: no effect; read: Reserved iv 35 interrupt disabled
#0
1
write: disable Reserved iv 35 interrupt; read: Reserved iv 35 interrupt enabled
#1
CLRENA2
no description available
2
1
read-write
0
write: no effect; read: DMA channel 2 transfer complete interrupt disabled
#0
1
write: disable DMA channel 2 transfer complete interrupt; read: DMA channel 2 transfer complete interrupt enabled
#1
CLRENA20
no description available
20
1
read-write
0
write: no effect; read: Real-time counter interrupt disabled
#0
1
write: disable Real-time counter interrupt; read: Real-time counter interrupt enabled
#1
CLRENA21
no description available
21
1
read-write
0
write: no effect; read: RTC seconds interrupt disabled
#0
1
write: disable RTC seconds interrupt; read: RTC seconds interrupt enabled
#1
CLRENA22
no description available
22
1
read-write
0
write: no effect; read: Periodic Interrupt Timer interrupt disabled
#0
1
write: disable Periodic Interrupt Timer interrupt; read: Periodic Interrupt Timer interrupt enabled
#1
CLRENA23
no description available
23
1
read-write
0
write: no effect; read: Reserved iv 39 interrupt disabled
#0
1
write: disable Reserved iv 39 interrupt; read: Reserved iv 39 interrupt enabled
#1
CLRENA24
no description available
24
1
read-write
0
write: no effect; read: Reserved iv 40 interrupt disabled
#0
1
write: disable Reserved iv 40 interrupt; read: Reserved iv 40 interrupt enabled
#1
CLRENA25
no description available
25
1
read-write
0
write: no effect; read: Reserved iv 41 interrupt disabled
#0
1
write: disable Reserved iv 41 interrupt; read: Reserved iv 41 interrupt enabled
#1
CLRENA26
no description available
26
1
read-write
0
write: no effect; read: Reserved iv 42 interrupt disabled
#0
1
write: disable Reserved iv 42 interrupt; read: Reserved iv 42 interrupt enabled
#1
CLRENA27
no description available
27
1
read-write
0
write: no effect; read: Multipurpose Clock Generator interrupt disabled
#0
1
write: disable Multipurpose Clock Generator interrupt; read: Multipurpose Clock Generator interrupt enabled
#1
CLRENA28
no description available
28
1
read-write
0
write: no effect; read: Low-Power Timer interrupt disabled
#0
1
write: disable Low-Power Timer interrupt; read: Low-Power Timer interrupt enabled
#1
CLRENA29
no description available
29
1
read-write
0
write: no effect; read: Reserved iv 45 interrupt disabled
#0
1
write: disable Reserved iv 45 interrupt; read: Reserved iv 45 interrupt enabled
#1
CLRENA3
no description available
3
1
read-write
0
write: no effect; read: DMA channel 3 transfer complete interrupt disabled
#0
1
write: disable DMA channel 3 transfer complete interrupt; read: DMA channel 3 transfer complete interrupt enabled
#1
CLRENA30
no description available
30
1
read-write
0
write: no effect; read: PORTA Pin detect interrupt disabled
#0
1
write: disable PORTA Pin detect interrupt; read: PORTA Pin detect interrupt enabled
#1
CLRENA31
no description available
31
1
read-write
0
write: no effect; read: PORTB Pin detect interrupt disabled
#0
1
write: disable PORTB Pin detect interrupt; read: PORTB Pin detect interrupt enabled
#1
CLRENA4
no description available
4
1
read-write
0
write: no effect; read: Reserved iv 20 interrupt disabled
#0
1
write: disable Reserved iv 20 interrupt; read: Reserved iv 20 interrupt enabled
#1
CLRENA5
no description available
5
1
read-write
0
write: no effect; read: Command complete and read collision interrupt disabled
#0
1
write: disable Command complete and read collision interrupt; read: Command complete and read collision interrupt enabled
#1
CLRENA6
no description available
6
1
read-write
0
write: no effect; read: Low-voltage detect, low-voltage warning interrupt disabled
#0
1
write: disable Low-voltage detect, low-voltage warning interrupt; read: Low-voltage detect, low-voltage warning interrupt enabled
#1
CLRENA7
no description available
7
1
read-write
0
write: no effect; read: Low Leakage Wakeup interrupt disabled
#0
1
write: disable Low Leakage Wakeup interrupt; read: Low Leakage Wakeup interrupt enabled
#1
CLRENA8
no description available
8
1
read-write
0
write: no effect; read: Inter-Integrated Circuit 0 interrupt disabled
#0
1
write: disable Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt enabled
#1
CLRENA9
no description available
9
1
read-write
0
write: no effect; read: Reserved iv 25 interrupt disabled
#0
1
write: disable Reserved iv 25 interrupt; read: Reserved iv 25 interrupt enabled
#1
ICPR
Interrupt Clear Pending Register
0x180
32
read-write
n
0x0
0x0
CLRPEND0
no description available
0
1
read-write
0
write: no effect; read: DMA channel 0 transfer complete interrupt is not pending
#0
1
write: removes pending state from the DMA channel 0 transfer complete interrupt; read: DMA channel 0 transfer complete interrupt is pending
#1
CLRPEND1
no description available
1
1
read-write
0
write: no effect; read: DMA channel 1 transfer complete interrupt is not pending
#0
1
write: removes pending state from the DMA channel 1 transfer complete interrupt; read: DMA channel 1 transfer complete interrupt is pending
#1
CLRPEND10
no description available
10
1
read-write
0
write: no effect; read: Serial Peripheral Interface 0 interrupt is not pending
#0
1
write: removes pending state from the Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt is pending
#1
CLRPEND11
no description available
11
1
read-write
0
write: no effect; read: Reserved iv 27 interrupt is not pending
#0
1
write: removes pending state from the Reserved iv 27 interrupt; read: Reserved iv 27 interrupt is pending
#1
CLRPEND12
no description available
12
1
read-write
0
write: no effect; read: UART0 status and error interrupt is not pending
#0
1
write: removes pending state from the UART0 status and error interrupt; read: UART0 status and error interrupt is pending
#1
CLRPEND13
no description available
13
1
read-write
0
write: no effect; read: Reserved iv 29 interrupt is not pending
#0
1
write: removes pending state from the Reserved iv 29 interrupt; read: Reserved iv 29 interrupt is pending
#1
CLRPEND14
no description available
14
1
read-write
0
write: no effect; read: Reserved iv 30 interrupt is not pending
#0
1
write: removes pending state from the Reserved iv 30 interrupt; read: Reserved iv 30 interrupt is pending
#1
CLRPEND15
no description available
15
1
read-write
0
write: no effect; read: Analog-to-Digital Converter 0 interrupt is not pending
#0
1
write: removes pending state from the Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt is pending
#1
CLRPEND16
no description available
16
1
read-write
0
write: no effect; read: Comparator 0 interrupt is not pending
#0
1
write: removes pending state from the Comparator 0 interrupt; read: Comparator 0 interrupt is pending
#1
CLRPEND17
no description available
17
1
read-write
0
write: no effect; read: Timer/PWM module 0 interrupt is not pending
#0
1
write: removes pending state from the Timer/PWM module 0 interrupt; read: Timer/PWM module 0 interrupt is pending
#1
CLRPEND18
no description available
18
1
read-write
0
write: no effect; read: Timer/PWM module 1 interrupt is not pending
#0
1
write: removes pending state from the Timer/PWM module 1 interrupt; read: Timer/PWM module 1 interrupt is pending
#1
CLRPEND19
no description available
19
1
read-write
0
write: no effect; read: Reserved iv 35 interrupt is not pending
#0
1
write: removes pending state from the Reserved iv 35 interrupt; read: Reserved iv 35 interrupt is pending
#1
CLRPEND2
no description available
2
1
read-write
0
write: no effect; read: DMA channel 2 transfer complete interrupt is not pending
#0
1
write: removes pending state from the DMA channel 2 transfer complete interrupt; read: DMA channel 2 transfer complete interrupt is pending
#1
CLRPEND20
no description available
20
1
read-write
0
write: no effect; read: Real-time counter interrupt is not pending
#0
1
write: removes pending state from the Real-time counter interrupt; read: Real-time counter interrupt is pending
#1
CLRPEND21
no description available
21
1
read-write
0
write: no effect; read: RTC seconds interrupt is not pending
#0
1
write: removes pending state from the RTC seconds interrupt; read: RTC seconds interrupt is pending
#1
CLRPEND22
no description available
22
1
read-write
0
write: no effect; read: Periodic Interrupt Timer interrupt is not pending
#0
1
write: removes pending state from the Periodic Interrupt Timer interrupt; read: Periodic Interrupt Timer interrupt is pending
#1
CLRPEND23
no description available
23
1
read-write
0
write: no effect; read: Reserved iv 39 interrupt is not pending
#0
1
write: removes pending state from the Reserved iv 39 interrupt; read: Reserved iv 39 interrupt is pending
#1
CLRPEND24
no description available
24
1
read-write
0
write: no effect; read: Reserved iv 40 interrupt is not pending
#0
1
write: removes pending state from the Reserved iv 40 interrupt; read: Reserved iv 40 interrupt is pending
#1
CLRPEND25
no description available
25
1
read-write
0
write: no effect; read: Reserved iv 41 interrupt is not pending
#0
1
write: removes pending state from the Reserved iv 41 interrupt; read: Reserved iv 41 interrupt is pending
#1
CLRPEND26
no description available
26
1
read-write
0
write: no effect; read: Reserved iv 42 interrupt is not pending
#0
1
write: removes pending state from the Reserved iv 42 interrupt; read: Reserved iv 42 interrupt is pending
#1
CLRPEND27
no description available
27
1
read-write
0
write: no effect; read: Multipurpose Clock Generator interrupt is not pending
#0
1
write: removes pending state from the Multipurpose Clock Generator interrupt; read: Multipurpose Clock Generator interrupt is pending
#1
CLRPEND28
no description available
28
1
read-write
0
write: no effect; read: Low-Power Timer interrupt is not pending
#0
1
write: removes pending state from the Low-Power Timer interrupt; read: Low-Power Timer interrupt is pending
#1
CLRPEND29
no description available
29
1
read-write
0
write: no effect; read: Reserved iv 45 interrupt is not pending
#0
1
write: removes pending state from the Reserved iv 45 interrupt; read: Reserved iv 45 interrupt is pending
#1
CLRPEND3
no description available
3
1
read-write
0
write: no effect; read: DMA channel 3 transfer complete interrupt is not pending
#0
1
write: removes pending state from the DMA channel 3 transfer complete interrupt; read: DMA channel 3 transfer complete interrupt is pending
#1
CLRPEND30
no description available
30
1
read-write
0
write: no effect; read: PORTA Pin detect interrupt is not pending
#0
1
write: removes pending state from the PORTA Pin detect interrupt; read: PORTA Pin detect interrupt is pending
#1
CLRPEND31
no description available
31
1
read-write
0
write: no effect; read: PORTB Pin detect interrupt is not pending
#0
1
write: removes pending state from the PORTB Pin detect interrupt; read: PORTB Pin detect interrupt is pending
#1
CLRPEND4
no description available
4
1
read-write
0
write: no effect; read: Reserved iv 20 interrupt is not pending
#0
1
write: removes pending state from the Reserved iv 20 interrupt; read: Reserved iv 20 interrupt is pending
#1
CLRPEND5
no description available
5
1
read-write
0
write: no effect; read: Command complete and read collision interrupt is not pending
#0
1
write: removes pending state from the Command complete and read collision interrupt; read: Command complete and read collision interrupt is pending
#1
CLRPEND6
no description available
6
1
read-write
0
write: no effect; read: Low-voltage detect, low-voltage warning interrupt is not pending
#0
1
write: removes pending state from the Low-voltage detect, low-voltage warning interrupt; read: Low-voltage detect, low-voltage warning interrupt is pending
#1
CLRPEND7
no description available
7
1
read-write
0
write: no effect; read: Low Leakage Wakeup interrupt is not pending
#0
1
write: removes pending state from the Low Leakage Wakeup interrupt; read: Low Leakage Wakeup interrupt is pending
#1
CLRPEND8
no description available
8
1
read-write
0
write: no effect; read: Inter-Integrated Circuit 0 interrupt is not pending
#0
1
write: removes pending state from the Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt is pending
#1
CLRPEND9
no description available
9
1
read-write
0
write: no effect; read: Reserved iv 25 interrupt is not pending
#0
1
write: removes pending state from the Reserved iv 25 interrupt; read: Reserved iv 25 interrupt is pending
#1
IPR0
Interrupt Priority Register 0
0x300
32
read-write
n
0x0
0x0
PRI_0
Priority of the DMA channel 0 transfer complete interrupt
6
2
read-write
PRI_1
Priority of the DMA channel 1 transfer complete interrupt
14
2
read-write
PRI_2
Priority of the DMA channel 2 transfer complete interrupt
22
2
read-write
PRI_3
Priority of the DMA channel 3 transfer complete interrupt
30
2
read-write
IPR1
Interrupt Priority Register 1
0x304
32
read-write
n
0x0
0x0
PRI_4
Priority of the Reserved iv 20 interrupt
6
2
read-write
PRI_5
Priority of the Command complete and read collision interrupt
14
2
read-write
PRI_6
Priority of the Low-voltage detect, low-voltage warning interrupt
22
2
read-write
PRI_7
Priority of the Low Leakage Wakeup interrupt
30
2
read-write
IPR2
Interrupt Priority Register 2
0x308
32
read-write
n
0x0
0x0
PRI_10
Priority of the Serial Peripheral Interface 0 interrupt
22
2
read-write
PRI_11
Priority of the Reserved iv 27 interrupt
30
2
read-write
PRI_8
Priority of the Inter-Integrated Circuit 0 interrupt
6
2
read-write
PRI_9
Priority of the Reserved iv 25 interrupt
14
2
read-write
IPR3
Interrupt Priority Register 3
0x30C
32
read-write
n
0x0
0x0
PRI_12
Priority of the UART0 status and error interrupt
6
2
read-write
PRI_13
Priority of the Reserved iv 29 interrupt
14
2
read-write
PRI_14
Priority of the Reserved iv 30 interrupt
22
2
read-write
PRI_15
Priority of the Analog-to-Digital Converter 0 interrupt
30
2
read-write
IPR4
Interrupt Priority Register 4
0x310
32
read-write
n
0x0
0x0
PRI_16
Priority of the Comparator 0 interrupt
6
2
read-write
PRI_17
Priority of the Timer/PWM module 0 interrupt
14
2
read-write
PRI_18
Priority of the Timer/PWM module 1 interrupt
22
2
read-write
PRI_19
Priority of the Reserved iv 35 interrupt
30
2
read-write
IPR5
Interrupt Priority Register 5
0x314
32
read-write
n
0x0
0x0
PRI_20
Priority of the Real-time counter interrupt
6
2
read-write
PRI_21
Priority of the RTC seconds interrupt
14
2
read-write
PRI_22
Priority of the Periodic Interrupt Timer interrupt
22
2
read-write
PRI_23
Priority of the Reserved iv 39 interrupt
30
2
read-write
IPR6
Interrupt Priority Register 6
0x318
32
read-write
n
0x0
0x0
PRI_24
Priority of the Reserved iv 40 interrupt
6
2
read-write
PRI_25
Priority of the Reserved iv 41 interrupt
14
2
read-write
PRI_26
Priority of the Reserved iv 42 interrupt
22
2
read-write
PRI_27
Priority of the Multipurpose Clock Generator interrupt
30
2
read-write
IPR7
Interrupt Priority Register 7
0x31C
32
read-write
n
0x0
0x0
PRI_28
Priority of the Low-Power Timer interrupt
6
2
read-write
PRI_29
Priority of the Reserved iv 45 interrupt
14
2
read-write
PRI_30
Priority of the PORTA Pin detect interrupt
22
2
read-write
PRI_31
Priority of the PORTB Pin detect interrupt
30
2
read-write
ISER
Interrupt Set Enable Register
0x0
32
read-write
n
0x0
0x0
SETENA0
no description available
0
1
read-write
0
write: no effect; read: DMA channel 0 transfer complete interrupt disabled
#0
1
write: enable DMA channel 0 transfer complete interrupt; read: DMA channel 0 transfer complete interrupt enabled
#1
SETENA1
no description available
1
1
read-write
0
write: no effect; read: DMA channel 1 transfer complete interrupt disabled
#0
1
write: enable DMA channel 1 transfer complete interrupt; read: DMA channel 1 transfer complete interrupt enabled
#1
SETENA10
no description available
10
1
read-write
0
write: no effect; read: Serial Peripheral Interface 0 interrupt disabled
#0
1
write: enable Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt enabled
#1
SETENA11
no description available
11
1
read-write
0
write: no effect; read: Reserved iv 27 interrupt disabled
#0
1
write: enable Reserved iv 27 interrupt; read: Reserved iv 27 interrupt enabled
#1
SETENA12
no description available
12
1
read-write
0
write: no effect; read: UART0 status and error interrupt disabled
#0
1
write: enable UART0 status and error interrupt; read: UART0 status and error interrupt enabled
#1
SETENA13
no description available
13
1
read-write
0
write: no effect; read: Reserved iv 29 interrupt disabled
#0
1
write: enable Reserved iv 29 interrupt; read: Reserved iv 29 interrupt enabled
#1
SETENA14
no description available
14
1
read-write
0
write: no effect; read: Reserved iv 30 interrupt disabled
#0
1
write: enable Reserved iv 30 interrupt; read: Reserved iv 30 interrupt enabled
#1
SETENA15
no description available
15
1
read-write
0
write: no effect; read: Analog-to-Digital Converter 0 interrupt disabled
#0
1
write: enable Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt enabled
#1
SETENA16
no description available
16
1
read-write
0
write: no effect; read: Comparator 0 interrupt disabled
#0
1
write: enable Comparator 0 interrupt; read: Comparator 0 interrupt enabled
#1
SETENA17
no description available
17
1
read-write
0
write: no effect; read: Timer/PWM module 0 interrupt disabled
#0
1
write: enable Timer/PWM module 0 interrupt; read: Timer/PWM module 0 interrupt enabled
#1
SETENA18
no description available
18
1
read-write
0
write: no effect; read: Timer/PWM module 1 interrupt disabled
#0
1
write: enable Timer/PWM module 1 interrupt; read: Timer/PWM module 1 interrupt enabled
#1
SETENA19
no description available
19
1
read-write
0
write: no effect; read: Reserved iv 35 interrupt disabled
#0
1
write: enable Reserved iv 35 interrupt; read: Reserved iv 35 interrupt enabled
#1
SETENA2
no description available
2
1
read-write
0
write: no effect; read: DMA channel 2 transfer complete interrupt disabled
#0
1
write: enable DMA channel 2 transfer complete interrupt; read: DMA channel 2 transfer complete interrupt enabled
#1
SETENA20
no description available
20
1
read-write
0
write: no effect; read: Real-time counter interrupt disabled
#0
1
write: enable Real-time counter interrupt; read: Real-time counter interrupt enabled
#1
SETENA21
no description available
21
1
read-write
0
write: no effect; read: RTC seconds interrupt disabled
#0
1
write: enable RTC seconds interrupt; read: RTC seconds interrupt enabled
#1
SETENA22
no description available
22
1
read-write
0
write: no effect; read: Periodic Interrupt Timer interrupt disabled
#0
1
write: enable Periodic Interrupt Timer interrupt; read: Periodic Interrupt Timer interrupt enabled
#1
SETENA23
no description available
23
1
read-write
0
write: no effect; read: Reserved iv 39 interrupt disabled
#0
1
write: enable Reserved iv 39 interrupt; read: Reserved iv 39 interrupt enabled
#1
SETENA24
no description available
24
1
read-write
0
write: no effect; read: Reserved iv 40 interrupt disabled
#0
1
write: enable Reserved iv 40 interrupt; read: Reserved iv 40 interrupt enabled
#1
SETENA25
no description available
25
1
read-write
0
write: no effect; read: Reserved iv 41 interrupt disabled
#0
1
write: enable Reserved iv 41 interrupt; read: Reserved iv 41 interrupt enabled
#1
SETENA26
no description available
26
1
read-write
0
write: no effect; read: Reserved iv 42 interrupt disabled
#0
1
write: enable Reserved iv 42 interrupt; read: Reserved iv 42 interrupt enabled
#1
SETENA27
no description available
27
1
read-write
0
write: no effect; read: Multipurpose Clock Generator interrupt disabled
#0
1
write: enable Multipurpose Clock Generator interrupt; read: Multipurpose Clock Generator interrupt enabled
#1
SETENA28
no description available
28
1
read-write
0
write: no effect; read: Low-Power Timer interrupt disabled
#0
1
write: enable Low-Power Timer interrupt; read: Low-Power Timer interrupt enabled
#1
SETENA29
no description available
29
1
read-write
0
write: no effect; read: Reserved iv 45 interrupt disabled
#0
1
write: enable Reserved iv 45 interrupt; read: Reserved iv 45 interrupt enabled
#1
SETENA3
no description available
3
1
read-write
0
write: no effect; read: DMA channel 3 transfer complete interrupt disabled
#0
1
write: enable DMA channel 3 transfer complete interrupt; read: DMA channel 3 transfer complete interrupt enabled
#1
SETENA30
no description available
30
1
read-write
0
write: no effect; read: PORTA Pin detect interrupt disabled
#0
1
write: enable PORTA Pin detect interrupt; read: PORTA Pin detect interrupt enabled
#1
SETENA31
no description available
31
1
read-write
0
write: no effect; read: PORTB Pin detect interrupt disabled
#0
1
write: enable PORTB Pin detect interrupt; read: PORTB Pin detect interrupt enabled
#1
SETENA4
no description available
4
1
read-write
0
write: no effect; read: Reserved iv 20 interrupt disabled
#0
1
write: enable Reserved iv 20 interrupt; read: Reserved iv 20 interrupt enabled
#1
SETENA5
no description available
5
1
read-write
0
write: no effect; read: Command complete and read collision interrupt disabled
#0
1
write: enable Command complete and read collision interrupt; read: Command complete and read collision interrupt enabled
#1
SETENA6
no description available
6
1
read-write
0
write: no effect; read: Low-voltage detect, low-voltage warning interrupt disabled
#0
1
write: enable Low-voltage detect, low-voltage warning interrupt; read: Low-voltage detect, low-voltage warning interrupt enabled
#1
SETENA7
no description available
7
1
read-write
0
write: no effect; read: Low Leakage Wakeup interrupt disabled
#0
1
write: enable Low Leakage Wakeup interrupt; read: Low Leakage Wakeup interrupt enabled
#1
SETENA8
no description available
8
1
read-write
0
write: no effect; read: Inter-Integrated Circuit 0 interrupt disabled
#0
1
write: enable Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt enabled
#1
SETENA9
no description available
9
1
read-write
0
write: no effect; read: Reserved iv 25 interrupt disabled
#0
1
write: enable Reserved iv 25 interrupt; read: Reserved iv 25 interrupt enabled
#1
ISPR
Interrupt Set Pending Register
0x100
32
read-write
n
0x0
0x0
SETPEND0
no description available
0
1
read-write
0
write: no effect; read: DMA channel 0 transfer complete interrupt is not pending
#0
1
write: changes the DMA channel 0 transfer complete interrupt state to pending; read: DMA channel 0 transfer complete interrupt is pending
#1
SETPEND1
no description available
1
1
read-write
0
write: no effect; read: DMA channel 1 transfer complete interrupt is not pending
#0
1
write: changes the DMA channel 1 transfer complete interrupt state to pending; read: DMA channel 1 transfer complete interrupt is pending
#1
SETPEND10
no description available
10
1
read-write
0
write: no effect; read: Serial Peripheral Interface 0 interrupt is not pending
#0
1
write: changes the Serial Peripheral Interface 0 interrupt state to pending; read: Serial Peripheral Interface 0 interrupt is pending
#1
SETPEND11
no description available
11
1
read-write
0
write: no effect; read: Reserved iv 27 interrupt is not pending
#0
1
write: changes the Reserved iv 27 interrupt state to pending; read: Reserved iv 27 interrupt is pending
#1
SETPEND12
no description available
12
1
read-write
0
write: no effect; read: UART0 status and error interrupt is not pending
#0
1
write: changes the UART0 status and error interrupt state to pending; read: UART0 status and error interrupt is pending
#1
SETPEND13
no description available
13
1
read-write
0
write: no effect; read: Reserved iv 29 interrupt is not pending
#0
1
write: changes the Reserved iv 29 interrupt state to pending; read: Reserved iv 29 interrupt is pending
#1
SETPEND14
no description available
14
1
read-write
0
write: no effect; read: Reserved iv 30 interrupt is not pending
#0
1
write: changes the Reserved iv 30 interrupt state to pending; read: Reserved iv 30 interrupt is pending
#1
SETPEND15
no description available
15
1
read-write
0
write: no effect; read: Analog-to-Digital Converter 0 interrupt is not pending
#0
1
write: changes the Analog-to-Digital Converter 0 interrupt state to pending; read: Analog-to-Digital Converter 0 interrupt is pending
#1
SETPEND16
no description available
16
1
read-write
0
write: no effect; read: Comparator 0 interrupt is not pending
#0
1
write: changes the Comparator 0 interrupt state to pending; read: Comparator 0 interrupt is pending
#1
SETPEND17
no description available
17
1
read-write
0
write: no effect; read: Timer/PWM module 0 interrupt is not pending
#0
1
write: changes the Timer/PWM module 0 interrupt state to pending; read: Timer/PWM module 0 interrupt is pending
#1
SETPEND18
no description available
18
1
read-write
0
write: no effect; read: Timer/PWM module 1 interrupt is not pending
#0
1
write: changes the Timer/PWM module 1 interrupt state to pending; read: Timer/PWM module 1 interrupt is pending
#1
SETPEND19
no description available
19
1
read-write
0
write: no effect; read: Reserved iv 35 interrupt is not pending
#0
1
write: changes the Reserved iv 35 interrupt state to pending; read: Reserved iv 35 interrupt is pending
#1
SETPEND2
no description available
2
1
read-write
0
write: no effect; read: DMA channel 2 transfer complete interrupt is not pending
#0
1
write: changes the DMA channel 2 transfer complete interrupt state to pending; read: DMA channel 2 transfer complete interrupt is pending
#1
SETPEND20
no description available
20
1
read-write
0
write: no effect; read: Real-time counter interrupt is not pending
#0
1
write: changes the Real-time counter interrupt state to pending; read: Real-time counter interrupt is pending
#1
SETPEND21
no description available
21
1
read-write
0
write: no effect; read: RTC seconds interrupt is not pending
#0
1
write: changes the RTC seconds interrupt state to pending; read: RTC seconds interrupt is pending
#1
SETPEND22
no description available
22
1
read-write
0
write: no effect; read: Periodic Interrupt Timer interrupt is not pending
#0
1
write: changes the Periodic Interrupt Timer interrupt state to pending; read: Periodic Interrupt Timer interrupt is pending
#1
SETPEND23
no description available
23
1
read-write
0
write: no effect; read: Reserved iv 39 interrupt is not pending
#0
1
write: changes the Reserved iv 39 interrupt state to pending; read: Reserved iv 39 interrupt is pending
#1
SETPEND24
no description available
24
1
read-write
0
write: no effect; read: Reserved iv 40 interrupt is not pending
#0
1
write: changes the Reserved iv 40 interrupt state to pending; read: Reserved iv 40 interrupt is pending
#1
SETPEND25
no description available
25
1
read-write
0
write: no effect; read: Reserved iv 41 interrupt is not pending
#0
1
write: changes the Reserved iv 41 interrupt state to pending; read: Reserved iv 41 interrupt is pending
#1
SETPEND26
no description available
26
1
read-write
0
write: no effect; read: Reserved iv 42 interrupt is not pending
#0
1
write: changes the Reserved iv 42 interrupt state to pending; read: Reserved iv 42 interrupt is pending
#1
SETPEND27
no description available
27
1
read-write
0
write: no effect; read: Multipurpose Clock Generator interrupt is not pending
#0
1
write: changes the Multipurpose Clock Generator interrupt state to pending; read: Multipurpose Clock Generator interrupt is pending
#1
SETPEND28
no description available
28
1
read-write
0
write: no effect; read: Low-Power Timer interrupt is not pending
#0
1
write: changes the Low-Power Timer interrupt state to pending; read: Low-Power Timer interrupt is pending
#1
SETPEND29
no description available
29
1
read-write
0
write: no effect; read: Reserved iv 45 interrupt is not pending
#0
1
write: changes the Reserved iv 45 interrupt state to pending; read: Reserved iv 45 interrupt is pending
#1
SETPEND3
no description available
3
1
read-write
0
write: no effect; read: DMA channel 3 transfer complete interrupt is not pending
#0
1
write: changes the DMA channel 3 transfer complete interrupt state to pending; read: DMA channel 3 transfer complete interrupt is pending
#1
SETPEND30
no description available
30
1
read-write
0
write: no effect; read: PORTA Pin detect interrupt is not pending
#0
1
write: changes the PORTA Pin detect interrupt state to pending; read: PORTA Pin detect interrupt is pending
#1
SETPEND31
no description available
31
1
read-write
0
write: no effect; read: PORTB Pin detect interrupt is not pending
#0
1
write: changes the PORTB Pin detect interrupt state to pending; read: PORTB Pin detect interrupt is pending
#1
SETPEND4
no description available
4
1
read-write
0
write: no effect; read: Reserved iv 20 interrupt is not pending
#0
1
write: changes the Reserved iv 20 interrupt state to pending; read: Reserved iv 20 interrupt is pending
#1
SETPEND5
no description available
5
1
read-write
0
write: no effect; read: Command complete and read collision interrupt is not pending
#0
1
write: changes the Command complete and read collision interrupt state to pending; read: Command complete and read collision interrupt is pending
#1
SETPEND6
no description available
6
1
read-write
0
write: no effect; read: Low-voltage detect, low-voltage warning interrupt is not pending
#0
1
write: changes the Low-voltage detect, low-voltage warning interrupt state to pending; read: Low-voltage detect, low-voltage warning interrupt is pending
#1
SETPEND7
no description available
7
1
read-write
0
write: no effect; read: Low Leakage Wakeup interrupt is not pending
#0
1
write: changes the Low Leakage Wakeup interrupt state to pending; read: Low Leakage Wakeup interrupt is pending
#1
SETPEND8
no description available
8
1
read-write
0
write: no effect; read: Inter-Integrated Circuit 0 interrupt is not pending
#0
1
write: changes the Inter-Integrated Circuit 0 interrupt state to pending; read: Inter-Integrated Circuit 0 interrupt is pending
#1
SETPEND9
no description available
9
1
read-write
0
write: no effect; read: Reserved iv 25 interrupt is not pending
#0
1
write: changes the Reserved iv 25 interrupt state to pending; read: Reserved iv 25 interrupt is pending
#1
OSC0
Oscillator
OSC0
0x0
0x0
0x1
registers
n
CR
OSC Control Register
0x0
8
read-write
n
0x0
0x0
ERCLKEN
External Reference Enable
7
1
read-write
0
External reference clock is inactive.
#0
1
External reference clock is enabled.
#1
EREFSTEN
External Reference Stop Enable
5
1
read-write
0
External reference clock is disabled in Stop mode.
#0
1
External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode.
#1
RESERVED
no description available
4
1
read-only
RESERVED
no description available
6
1
read-only
SC16P
Oscillator 16 pF Capacitor Load Configure
0
1
read-write
0
Disable the selection.
#0
1
Add 16 pF capacitor to the oscillator load.
#1
SC2P
Oscillator 2 pF Capacitor Load Configure
3
1
read-write
0
Disable the selection.
#0
1
Add 2 pF capacitor to the oscillator load.
#1
SC4P
Oscillator 4 pF Capacitor Load Configure
2
1
read-write
0
Disable the selection.
#0
1
Add 4 pF capacitor to the oscillator load.
#1
SC8P
Oscillator 8 pF Capacitor Load Configure
1
1
read-write
0
Disable the selection.
#0
1
Add 8 pF capacitor to the oscillator load.
#1
PIT
Periodic Interrupt Timer
PIT
0x0
0x0
0x120
registers
n
PIT
22
INT_PIT
22
CVAL0
Current Timer Value Register
0x208
32
read-only
n
0x0
0x0
TVL
Current Timer Value
0
32
read-only
CVAL1
Current Timer Value Register
0x31C
32
read-only
n
0x0
0x0
TVL
Current Timer Value
0
32
read-only
LDVAL0
Timer Load Value Register
0x200
32
read-write
n
0x0
0x0
TSV
Timer Start Value
0
32
read-write
LDVAL1
Timer Load Value Register
0x310
32
read-write
n
0x0
0x0
TSV
Timer Start Value
0
32
read-write
LTMR64H
PIT Upper Lifetime Timer Register
0xE0
32
read-only
n
0x0
0x0
LTH
Life Timer value
0
32
read-only
LTMR64L
PIT Lower Lifetime Timer Register
0xE4
32
read-only
n
0x0
0x0
LTL
Life Timer value
0
32
read-only
MCR
PIT Module Control Register
0x0
32
read-write
n
0x0
0x0
FRZ
Freeze
0
1
read-write
0
Timers continue to run in Debug mode.
#0
1
Timers are stopped in Debug mode.
#1
MDIS
Module Disable - (PIT section)
1
1
read-write
0
Clock for standard PIT timers is enabled.
#0
1
Clock for standard PIT timers is disabled.
#1
RESERVED
no description available
2
1
read-only
RESERVED
no description available
3
29
read-only
TCTRL0
Timer Control Register
0x210
32
read-write
n
0x0
0x0
CHN
Chain Mode
2
1
read-write
0
Timer is not chained.
#0
1
Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
#1
RESERVED
no description available
3
29
read-only
TEN
Timer Enable
0
1
read-write
0
Timer n is disabled.
#0
1
Timer n is enabled.
#1
TIE
Timer Interrupt Enable
1
1
read-write
0
Interrupt requests from Timer n are disabled.
#0
1
Interrupt will be requested whenever TIF is set.
#1
TCTRL1
Timer Control Register
0x328
32
read-write
n
0x0
0x0
CHN
Chain Mode
2
1
read-write
0
Timer is not chained.
#0
1
Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
#1
RESERVED
no description available
3
29
read-only
TEN
Timer Enable
0
1
read-write
0
Timer n is disabled.
#0
1
Timer n is enabled.
#1
TIE
Timer Interrupt Enable
1
1
read-write
0
Interrupt requests from Timer n are disabled.
#0
1
Interrupt will be requested whenever TIF is set.
#1
TFLG0
Timer Flag Register
0x218
32
read-write
n
0x0
0x0
RESERVED
no description available
1
31
read-only
TIF
Timer Interrupt Flag
0
1
read-write
0
Timeout has not yet occurred.
#0
1
Timeout has occurred.
#1
TFLG1
Timer Flag Register
0x334
32
read-write
n
0x0
0x0
RESERVED
no description available
1
31
read-only
TIF
Timer Interrupt Flag
0
1
read-write
0
Timeout has not yet occurred.
#0
1
Timeout has occurred.
#1
PMC
Power Management Controller
PMC
0x0
0x0
0x3
registers
n
LVD_LVW
6
INT_LVD_LVW
6
LVDSC1
Low Voltage Detect Status And Control 1 register
0x0
8
read-write
n
0x0
0x0
LVDACK
Low-Voltage Detect Acknowledge
6
1
write-only
LVDF
Low-Voltage Detect Flag
7
1
read-only
0
Low-voltage event not detected
#0
1
Low-voltage event detected
#1
LVDIE
Low-Voltage Detect Interrupt Enable
5
1
read-write
0
Hardware interrupt disabled (use polling)
#0
1
Request a hardware interrupt when LVDF = 1
#1
LVDRE
Low-Voltage Detect Reset Enable
4
1
read-write
0
LVDF does not generate hardware resets
#0
1
Force an MCU reset when LVDF = 1
#1
LVDV
Low-Voltage Detect Voltage Select
0
2
read-write
00
Low trip point selected (V LVD = V LVDL )
#00
01
High trip point selected (V LVD = V LVDH )
#01
10
Reserved
#10
11
Reserved
#11
RESERVED
no description available
2
2
read-only
LVDSC2
Low Voltage Detect Status And Control 2 register
0x1
8
read-write
n
0x0
0x0
LVWACK
Low-Voltage Warning Acknowledge
6
1
write-only
LVWF
Low-Voltage Warning Flag
7
1
read-only
0
Low-voltage warning event not detected
#0
1
Low-voltage warning event detected
#1
LVWIE
Low-Voltage Warning Interrupt Enable
5
1
read-write
0
Hardware interrupt disabled (use polling)
#0
1
Request a hardware interrupt when LVWF = 1
#1
LVWV
Low-Voltage Warning Voltage Select
0
2
read-write
00
Low trip point selected (VLVW = VLVW1)
#00
01
Mid 1 trip point selected (VLVW = VLVW2)
#01
10
Mid 2 trip point selected (VLVW = VLVW3)
#10
11
High trip point selected (VLVW = VLVW4)
#11
RESERVED
no description available
2
3
read-only
REGSC
Regulator Status And Control register
0x2
8
read-write
n
0x0
0x0
ACKISO
Acknowledge Isolation
3
1
read-write
0
Peripherals and I/O pads are in normal run state
#0
1
Certain peripherals and I/O pads are in an isolated and latched state
#1
BGBE
Bandgap Buffer Enable
0
1
read-write
0
Bandgap buffer not enabled
#0
1
Bandgap buffer enabled
#1
BGEN
Bandgap Enable In VLPx Operation
4
1
read-write
0
Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes
#0
1
Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes
#1
REGONS
Regulator In Run Regulation Status
2
1
read-only
0
Regulator is in stop regulation or in transition to/from it
#0
1
Regulator is in run regulation
#1
RESERVED
no description available
1
1
read-write
RESERVED
no description available
5
1
read-write
RESERVED
no description available
6
2
read-only
PORTA
Pin Control and Interrupts
PORT
0x0
0x0
0xA4
registers
n
PORTA
30
GPCHR
Global Pin Control High Register
0x84
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPCLR
Global Pin Control Low Register
0x80
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
ISFR
Interrupt Status Flag Register
0xA0
32
read-write
n
0x0
0x0
ISF
Interrupt Status Flag
0
32
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR0
Pin Control Register n
0x0
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR1
Pin Control Register n
0x4
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR10
Pin Control Register n
0xDC
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR11
Pin Control Register n
0x108
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR12
Pin Control Register n
0x138
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR13
Pin Control Register n
0x16C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR14
Pin Control Register n
0x1A4
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR15
Pin Control Register n
0x1E0
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR16
Pin Control Register n
0x220
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR17
Pin Control Register n
0x264
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR18
Pin Control Register n
0x2AC
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR19
Pin Control Register n
0x2F8
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR2
Pin Control Register n
0xC
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR20
Pin Control Register n
0x348
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR21
Pin Control Register n
0x39C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR22
Pin Control Register n
0x3F4
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR23
Pin Control Register n
0x450
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR24
Pin Control Register n
0x4B0
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR25
Pin Control Register n
0x514
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR26
Pin Control Register n
0x57C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR27
Pin Control Register n
0x5E8
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR28
Pin Control Register n
0x658
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR29
Pin Control Register n
0x6CC
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR3
Pin Control Register n
0x18
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR30
Pin Control Register n
0x744
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR31
Pin Control Register n
0x7C0
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR4
Pin Control Register n
0x28
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR5
Pin Control Register n
0x3C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR6
Pin Control Register n
0x54
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR7
Pin Control Register n
0x70
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR8
Pin Control Register n
0x90
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR9
Pin Control Register n
0xB4
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PORTB
Pin Control and Interrupts
PORT
0x0
0x0
0xA4
registers
n
PORTB
31
GPCHR
Global Pin Control High Register
0x84
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPCLR
Global Pin Control Low Register
0x80
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
ISFR
Interrupt Status Flag Register
0xA0
32
read-write
n
0x0
0x0
ISF
Interrupt Status Flag
0
32
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR0
Pin Control Register n
0x0
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR1
Pin Control Register n
0x4
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR10
Pin Control Register n
0xDC
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR11
Pin Control Register n
0x108
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR12
Pin Control Register n
0x138
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR13
Pin Control Register n
0x16C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR14
Pin Control Register n
0x1A4
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR15
Pin Control Register n
0x1E0
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR16
Pin Control Register n
0x220
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR17
Pin Control Register n
0x264
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR18
Pin Control Register n
0x2AC
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR19
Pin Control Register n
0x2F8
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR2
Pin Control Register n
0xC
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR20
Pin Control Register n
0x348
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR21
Pin Control Register n
0x39C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR22
Pin Control Register n
0x3F4
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR23
Pin Control Register n
0x450
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR24
Pin Control Register n
0x4B0
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR25
Pin Control Register n
0x514
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR26
Pin Control Register n
0x57C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR27
Pin Control Register n
0x5E8
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR28
Pin Control Register n
0x658
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR29
Pin Control Register n
0x6CC
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR3
Pin Control Register n
0x18
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR30
Pin Control Register n
0x744
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR31
Pin Control Register n
0x7C0
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR4
Pin Control Register n
0x28
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR5
Pin Control Register n
0x3C
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR6
Pin Control Register n
0x54
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR7
Pin Control Register n
0x70
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR8
Pin Control Register n
0x90
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR9
Pin Control Register n
0xB4
32
read-write
n
0x0
0x0
DSE
Drive Strength Enable
6
1
read-write
0
Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#0
1
High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
#1
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PFE
Passive Filter Enable
4
1
read-write
0
Passive input filter is disabled on the corresponding pin.
#0
1
Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
11
5
read-only
RESERVED
no description available
20
4
read-only
RESERVED
no description available
25
7
read-only
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PTA
General Purpose Input/Output
GPIO
0x0
0x0
0x18
registers
n
INT_PORTA
30
GPIOA_PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
GPIOA_PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
GPIOA_PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
GPIOA_PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
GPIOA_PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
GPIOA_PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTB
General Purpose Input/Output
GPIO
0x0
0x0
0x18
registers
n
INT_PORTB
31
GPIOB_PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
GPIOB_PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
GPIOB_PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
GPIOB_PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
GPIOB_PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
GPIOB_PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
RCM
Reset Control Module
RCM
0x0
0x0
0x6
registers
n
RPFC
Reset Pin Filter Control register
0x4
8
read-write
n
0x0
0x0
RESERVED
no description available
3
5
read-only
RSTFLTSRW
Reset Pin Filter Select in Run and Wait Modes
0
2
read-write
00
All filtering disabled
#00
01
Bus clock filter enabled for normal operation
#01
10
LPO clock filter enabled for normal operation
#10
11
Reserved
#11
RSTFLTSS
Reset Pin Filter Select in Stop Mode
2
1
read-write
0
All filtering disabled
#0
1
LPO clock filter enabled
#1
RPFW
Reset Pin Filter Width register
0x5
8
read-write
n
0x0
0x0
RESERVED
no description available
5
3
read-only
RSTFLTSEL
Reset Pin Filter Bus Clock Select
0
5
read-write
00000
Bus clock filter count is 1
#00000
00001
Bus clock filter count is 2
#00001
00010
Bus clock filter count is 3
#00010
00011
Bus clock filter count is 4
#00011
00100
Bus clock filter count is 5
#00100
00101
Bus clock filter count is 6
#00101
00110
Bus clock filter count is 7
#00110
00111
Bus clock filter count is 8
#00111
01000
Bus clock filter count is 9
#01000
01001
Bus clock filter count is 10
#01001
01010
Bus clock filter count is 11
#01010
01011
Bus clock filter count is 12
#01011
01100
Bus clock filter count is 13
#01100
01101
Bus clock filter count is 14
#01101
01110
Bus clock filter count is 15
#01110
01111
Bus clock filter count is 16
#01111
10000
Bus clock filter count is 17
#10000
10001
Bus clock filter count is 18
#10001
10010
Bus clock filter count is 19
#10010
10011
Bus clock filter count is 20
#10011
10100
Bus clock filter count is 21
#10100
10101
Bus clock filter count is 22
#10101
10110
Bus clock filter count is 23
#10110
10111
Bus clock filter count is 24
#10111
11000
Bus clock filter count is 25
#11000
11001
Bus clock filter count is 26
#11001
11010
Bus clock filter count is 27
#11010
11011
Bus clock filter count is 28
#11011
11100
Bus clock filter count is 29
#11100
11101
Bus clock filter count is 30
#11101
11110
Bus clock filter count is 31
#11110
11111
Bus clock filter count is 32
#11111
SRS0
System Reset Status Register 0
0x0
8
read-only
n
0x0
0x0
LOC
Loss-of-Clock Reset
2
1
read-only
0
Reset not caused by a loss of external clock.
#0
1
Reset caused by a loss of external clock.
#1
LVD
Low-Voltage Detect Reset
1
1
read-only
0
Reset not caused by LVD trip or POR
#0
1
Reset caused by LVD trip or POR
#1
PIN
External Reset Pin
6
1
read-only
0
Reset not caused by external reset pin
#0
1
Reset caused by external reset pin
#1
POR
Power-On Reset
7
1
read-only
0
Reset not caused by POR
#0
1
Reset caused by POR
#1
RESERVED
no description available
3
2
read-only
WAKEUP
Low Leakage Wakeup Reset
0
1
read-only
0
Reset not caused by LLWU module wakeup source
#0
1
Reset caused by LLWU module wakeup source
#1
WDOG
Watchdog
5
1
read-only
0
Reset not caused by watchdog timeout
#0
1
Reset caused by watchdog timeout
#1
SRS1
System Reset Status Register 1
0x1
8
read-only
n
0x0
0x0
LOCKUP
Core Lockup
1
1
read-only
0
Reset not caused by core LOCKUP event
#0
1
Reset caused by core LOCKUP event
#1
MDM_AP
MDM-AP System Reset Request
3
1
read-only
0
Reset not caused by host debugger system setting of the System Reset Request bit
#0
1
Reset caused by host debugger system setting of the System Reset Request bit
#1
RESERVED
no description available
0
1
read-only
RESERVED
no description available
4
1
read-only
RESERVED
no description available
6
1
read-only
RESERVED
no description available
7
1
read-only
SACKERR
Stop Mode Acknowledge Error Reset
5
1
read-only
0
Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
#0
1
Reset caused by peripheral failure to acknowledge attempt to enter stop mode
#1
SW
Software
2
1
read-only
0
Reset not caused by software setting of SYSRESETREQ bit
#0
1
Reset caused by software setting of SYSRESETREQ bit
#1
ROM
System ROM
ROM
0x0
0x0
0x1000
registers
n
COMPID0
Component ID Register
0x1FE0
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID1
Component ID Register
0x2FD4
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID2
Component ID Register
0x3FCC
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID3
Component ID Register
0x4FC8
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
ENTRY0
Entry
0x0
32
read-only
n
0x0
0x0
ENTRY
ENTRY
0
32
read-only
ENTRY1
Entry
0x4
32
read-only
n
0x0
0x0
ENTRY
ENTRY
0
32
read-only
ENTRY2
Entry
0xC
32
read-only
n
0x0
0x0
ENTRY
ENTRY
0
32
read-only
PERIPHID0
Peripheral ID Register
0x5F08
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID1
Peripheral ID Register
0x6EEC
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID2
Peripheral ID Register
0x7ED4
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID3
Peripheral ID Register
0x8EC0
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID4
Peripheral ID Register
0x1FA0
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID5
Peripheral ID Register
0x2F74
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID6
Peripheral ID Register
0x3F4C
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID7
Peripheral ID Register
0x4F28
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
SYSACCESS
System Access Register
0xFCC
32
read-only
n
0x0
0x0
SYSACCESS
no description available
0
32
read-only
TABLEMARK
End of Table Marker Register
0xC
32
read-only
n
0x0
0x0
MARK
no description available
0
32
read-only
RTC
Secure Real Time Clock
RTC
0x0
0x0
0x20
registers
n
0x0
0x20
registers
n
RTC
4
INT_RTC
20
RTC_Seconds
21
INT_RTC_Seconds
21
CR
RTC Control Register
0x10
32
read-write
n
0x0
0x0
CLKO
Clock Output
9
1
read-write
0
The 32 kHz clock is output to other peripherals.
#0
1
The 32 kHz clock is not output to other peripherals.
#1
OSCE
Oscillator Enable
8
1
read-write
0
32.768 kHz oscillator is disabled.
#0
1
32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.
#1
RESERVED
no description available
4
4
read-only
RESERVED
no description available
14
1
read-only
RESERVED
no description available
15
17
read-only
SC16P
Oscillator 16pF Load Configure
10
1
read-write
0
Disable the load.
#0
1
Enable the additional load.
#1
SC2P
Oscillator 2pF Load Configure
13
1
read-write
0
Disable the load.
#0
1
Enable the additional load.
#1
SC4P
Oscillator 4pF Load Configure
12
1
read-write
0
Disable the load.
#0
1
Enable the additional load.
#1
SC8P
Oscillator 8pF Load Configure
11
1
read-write
0
Disable the load.
#0
1
Enable the additional load.
#1
SUP
Supervisor Access
2
1
read-write
0
Non-supervisor mode write accesses are not supported and generate a bus error.
#0
1
Non-supervisor mode write accesses are supported.
#1
SWR
Software Reset
0
1
read-write
0
No effect.
#0
1
Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it.
#1
UM
Update Mode
3
1
read-write
0
Registers cannot be written when locked.
#0
1
Registers can be written when locked under limited conditions.
#1
WPE
Wakeup Pin Enable
1
1
read-write
0
Wakeup pin is disabled.
#0
1
Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on.
#1
IER
RTC Interrupt Enable Register
0x1C
32
read-write
n
0x0
0x0
RESERVED
no description available
3
1
read-write
RESERVED
no description available
5
2
read-write
RESERVED
no description available
8
24
read-only
TAIE
Time Alarm Interrupt Enable
2
1
read-write
0
Time alarm flag does not generate an interrupt.
#0
1
Time alarm flag does generate an interrupt.
#1
TIIE
Time Invalid Interrupt Enable
0
1
read-write
0
Time invalid flag does not generate an interrupt.
#0
1
Time invalid flag does generate an interrupt.
#1
TOIE
Time Overflow Interrupt Enable
1
1
read-write
0
Time overflow flag does not generate an interrupt.
#0
1
Time overflow flag does generate an interrupt.
#1
TSIE
Time Seconds Interrupt Enable
4
1
read-write
0
Seconds interrupt is disabled.
#0
1
Seconds interrupt is enabled.
#1
WPON
Wakeup Pin On
7
1
read-write
0
No effect.
#0
1
If the wakeup pin is enabled, then the wakeup pin will assert.
#1
LR
RTC Lock Register
0x18
32
read-write
n
0x0
0x0
CRL
Control Register Lock
4
1
read-write
0
Control Register is locked and writes are ignored.
#0
1
Control Register is not locked and writes complete as normal.
#1
LRL
Lock Register Lock
6
1
read-write
0
Lock Register is locked and writes are ignored.
#0
1
Lock Register is not locked and writes complete as normal.
#1
RESERVED
no description available
0
3
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
8
24
read-only
SRL
Status Register Lock
5
1
read-write
0
Status Register is locked and writes are ignored.
#0
1
Status Register is not locked and writes complete as normal.
#1
TCL
Time Compensation Lock
3
1
read-write
0
Time Compensation Register is locked and writes are ignored.
#0
1
Time Compensation Register is not locked and writes complete as normal.
#1
SR
RTC Status Register
0x14
32
read-write
n
0x0
0x0
RESERVED
no description available
3
1
read-only
RESERVED
no description available
5
27
read-only
TAF
Time Alarm Flag
2
1
read-only
0
Time alarm has not occurred.
#0
1
Time alarm has occurred.
#1
TCE
Time Counter Enable
4
1
read-write
0
Time counter is disabled.
#0
1
Time counter is enabled.
#1
TIF
Time Invalid Flag
0
1
read-only
0
Time is valid.
#0
1
Time is invalid and time counter is read as zero.
#1
TOF
Time Overflow Flag
1
1
read-only
0
Time overflow has not occurred.
#0
1
Time overflow has occurred and time counter is read as zero.
#1
TAR
RTC Time Alarm Register
0x8
32
read-write
n
0x0
0x0
TAR
Time Alarm Register
0
32
read-write
TCR
RTC Time Compensation Register
0xC
32
read-write
n
0x0
0x0
CIC
Compensation Interval Counter
24
8
read-only
CIR
Compensation Interval Register
8
8
read-write
TCR
Time Compensation Register
0
8
read-write
0
Time Prescaler Register overflows every 32768 clock cycles.
#0
1
Time Prescaler Register overflows every 32767 clock cycles.
#1
10000000
Time Prescaler Register overflows every 32896 clock cycles.
#10000000
1111111
Time Prescaler Register overflows every 32641 clock cycles.
#1111111
11111111
Time Prescaler Register overflows every 32769 clock cycles.
#11111111
TCV
Time Compensation Value
16
8
read-only
TPR
RTC Time Prescaler Register
0x4
32
read-write
n
0x0
0x0
RESERVED
no description available
16
16
read-only
TPR
Time Prescaler Register
0
16
read-write
TSR
RTC Time Seconds Register
0x0
32
read-write
n
0x0
0x0
TSR
Time Seconds Register
0
32
read-write
SIM
System Integration Module
SIM
0x0
0x0
0x1108
registers
n
CLKDIV1
System Clock Divider Register 1
0x1044
32
read-write
n
0x0
0x0
OUTDIV1
Clock 1 output divider value
28
4
read-write
0000
Divide-by-1.
#0000
0001
Divide-by-2.
#0001
0010
Divide-by-3.
#0010
0011
Divide-by-4.
#0011
0100
Divide-by-5.
#0100
0101
Divide-by-6.
#0101
0110
Divide-by-7.
#0110
0111
Divide-by-8.
#0111
1000
Divide-by-9.
#1000
1001
Divide-by-10.
#1001
1010
Divide-by-11.
#1010
1011
Divide-by-12.
#1011
1100
Divide-by-13.
#1100
1101
Divide-by-14.
#1101
1110
Divide-by-15.
#1110
1111
Divide-by-16.
#1111
OUTDIV4
Clock 4 output divider value
16
3
read-write
000
Divide-by-1.
#000
001
Divide-by-2.
#001
010
Divide-by-3.
#010
011
Divide-by-4.
#011
100
Divide-by-5.
#100
101
Divide-by-6.
#101
110
Divide-by-7.
#110
111
Divide-by-8.
#111
RESERVED
no description available
0
16
read-only
RESERVED
no description available
19
9
read-only
COPC
COP Control Register
0x1100
32
read-write
n
0x0
0x0
COPCLKS
COP Clock Select
1
1
read-write
0
Internal 1 kHz clock is source to COP
#0
1
Bus clock is source to COP
#1
COPT
COP Watchdog Timeout
2
2
read-write
00
COP disabled
#00
01
COP timeout after 2^5 LPO cycles or 213 bus clock cycles
#01
10
COP timeout after 2^8 LPO cycles or 216 bus clock cycles
#10
11
COP timeout after 2^10 LPO cycles or 218 bus clock cycles
#11
COPW
COP windowed mode
0
1
read-write
0
Normal mode
#0
1
Windowed mode
#1
RESERVED
no description available
4
28
read-only
FCFG1
Flash Configuration Register 1
0x104C
32
read-write
n
0x0
0x0
FLASHDIS
Flash Disable
0
1
read-write
0
Flash is enabled
#0
1
Flash is disabled
#1
FLASHDOZE
Flash Doze
1
1
read-write
0
Flash remains enabled during Doze mode
#0
1
Flash is disabled for the duration of Doze mode
#1
PFSIZE
Program flash size
24
4
read-only
0000
8 KB of program flash memory, 0.25 KB protection region
#0000
0001
16 KB of program flash memory, 0.5 KB protection region
#0001
0011
32 KB of program flash memory, 1 KB protection region
#0011
0101
64 KB of program flash memory, 2 KB protection region
#0101
0111
128 KB of program flash memory, 4 KB protection region
#0111
1001
256 KB of program flash memory, 8 KB protection region
#1001
1111
32 KB of program flash memory, 1 KB protection region
#1111
RESERVED
no description available
2
22
read-only
RESERVED
no description available
28
4
read-only
FCFG2
Flash Configuration Register 2
0x1050
32
read-only
n
0x0
0x0
MAXADDR0
Max address block
24
7
read-only
RESERVED
no description available
0
16
read-only
RESERVED
no description available
16
7
read-only
RESERVED
no description available
23
1
read-only
RESERVED
no description available
31
1
read-only
SCGC4
System Clock Gating Control Register 4
0x1034
32
read-write
n
0x0
0x0
CMP
Comparator Clock Gate Control
19
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
I2C0
I2C0 Clock Gate Control
6
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
RESERVED
no description available
0
4
read-only
RESERVED
no description available
4
2
read-only
RESERVED
no description available
7
1
read-only
RESERVED
no description available
8
2
read-only
RESERVED
no description available
11
1
read-only
RESERVED
no description available
12
1
read-only
RESERVED
no description available
13
1
read-only
RESERVED
no description available
14
4
read-only
RESERVED
no description available
18
1
read-only
RESERVED
no description available
20
2
read-only
RESERVED
no description available
23
1
read-only
RESERVED
no description available
24
4
read-only
RESERVED
no description available
28
4
read-only
SPI0
SPI0 Clock Gate Control
22
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
UART0
UART0 Clock Gate Control
10
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SCGC5
System Clock Gating Control Register 5
0x1038
32
read-write
n
0x0
0x0
LPTMR
Low Power Timer Access Control
0
1
read-write
0
Access disabled
#0
1
Access enabled
#1
PORTA
Port A Clock Gate Control
9
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PORTB
Port B Clock Gate Control
10
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
RESERVED
no description available
1
1
read-only
RESERVED
no description available
2
3
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
6
1
read-only
RESERVED
no description available
7
2
read-only
RESERVED
no description available
11
3
read-only
RESERVED
no description available
14
5
read-only
RESERVED
no description available
19
1
read-only
RESERVED
no description available
20
12
read-only
SCGC6
System Clock Gating Control Register 6
0x103C
32
read-write
n
0x0
0x0
ADC0
ADC0 Clock Gate Control
27
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
DMAMUX
DMA Mux Clock Gate Control
1
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
FTF
Flash Memory Clock Gate Control
0
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PIT
PIT Clock Gate Control
23
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
RESERVED
no description available
2
13
read-only
RESERVED
no description available
15
1
read-only
RESERVED
no description available
16
7
read-only
RESERVED
no description available
26
1
read-only
RESERVED
no description available
28
1
read-only
RESERVED
no description available
30
1
read-only
RESERVED
no description available
31
1
read-only
RTC
RTC Access Control
29
1
read-write
0
Access and interrupts disabled
#0
1
Access and interrupts enabled
#1
TPM0
TPM0 Clock Gate Control
24
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
TPM1
TPM1 Clock Gate Control
25
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SCGC7
System Clock Gating Control Register 7
0x1040
32
read-write
n
0x0
0x0
DMA
DMA Clock Gate Control
8
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
RESERVED
no description available
0
8
read-only
RESERVED
no description available
9
23
read-only
SDID
System Device Identification Register
0x1024
32
read-only
n
0x0
0x0
DIEID
Device die number
7
5
read-only
FAMID
Kinetis family ID
28
4
read-only
0000
KL0x Family (low end)
#0000
0001
KL1x Family (basic)
#0001
0010
KL2x Family (USB)
#0010
0011
KL3x Family (Segment LCD)
#0011
0100
KL4x Family (USB and Segment LCD)
#0100
PINID
Pincount identification
0
4
read-only
0000
16-pin
#0000
0001
24-pin
#0001
0010
32-pin
#0010
0011
Reserved
#0011
0100
48-pin
#0100
0101
64-pin
#0101
0110
80-pin
#0110
0111
Reserved
#0111
1000
100-pin
#1000
1001
Reserved
#1001
1010
Reserved
#1010
1011
Reserved
#1011
1100
Reserved
#1100
1101
Reserved
#1101
1110
Reserved
#1110
1111
Reserved
#1111
RESERVED
no description available
4
3
read-only
REVID
Device revision number
12
4
read-only
SERIESID
Kinetis Series ID
20
4
read-only
0001
KL family
#0001
SRAMSIZE
System SRAM Size
16
4
read-only
0000
0.5 KB
#0000
0001
1 KB
#0001
0010
2 KB
#0010
0011
4 KB
#0011
0100
8 KB
#0100
0101
16 KB
#0101
0110
32 KB
#0110
0111
64 KB
#0111
SUBFAMID
Kinetis Sub-Family ID
24
4
read-only
0010
KLx2 Subfamily (low end)
#0010
0100
KLx4 Subfamily (basic analog)
#0100
0101
KLx5 Subfamily (advanced analog)
#0101
0110
KLx6 Subfamily (advanced analog with I2S)
#0110
SOPT1
System Options Register 1
0x0
32
read-write
n
0x0
0x0
OSC32KSEL
32K oscillator clock select
18
2
read-write
00
System oscillator (OSC32KCLK)
#00
01
Reserved
#01
10
RTC_CLKIN
#10
11
LPO 1kHz
#11
RESERVED
no description available
0
18
read-only
RESERVED
no description available
20
12
read-only
SOPT1CFG
SOPT1 Configuration Register
0x4
32
read-only
n
0x0
0x0
RESERVED
no description available
0
24
read-only
RESERVED
no description available
24
8
read-only
SOPT2
System Options Register 2
0x1004
32
read-write
n
0x0
0x0
CLKOUTSEL
CLKOUT select
5
3
read-write
000
Reserved
#000
001
Reserved
#001
010
Bus clock
#010
011
LPO clock (1 kHz)
#011
100
MCGIRCLK
#100
101
Reserved
#101
110
OSCERCLK
#110
111
Reserved
#111
RESERVED
no description available
0
4
read-only
RESERVED
no description available
8
8
read-only
RESERVED
no description available
16
8
read-only
RESERVED
no description available
28
4
read-only
RTCCLKOUTSEL
RTC clock out select
4
1
read-write
0
RTC 1 Hz clock is output on the RTC_CLKOUT pin.
#0
1
OSCERCLK clock is output on the RTC_CLKOUT pin.
#1
TPMSRC
TPM clock source select
24
2
read-write
00
Clock disabled
#00
01
MCGFLLCLK clock
#01
10
OSCERCLK clock
#10
11
MCGIRCLK clock
#11
UART0SRC
UART0 clock source select
26
2
read-write
00
Clock disabled
#00
01
MCGFLLCLK clock
#01
10
OSCERCLK clock
#10
11
MCGIRCLK clock
#11
SOPT4
System Options Register 4
0x100C
32
read-write
n
0x0
0x0
RESERVED
no description available
0
18
read-only
RESERVED
no description available
19
1
read-only
RESERVED
no description available
20
1
read-only
RESERVED
no description available
21
3
read-only
RESERVED
no description available
26
1
read-only
RESERVED
no description available
27
5
read-only
TPM0CLKSEL
TPM0 External Clock Pin Select
24
1
read-write
0
TPM0 external clock driven by TPM_CLKIN0 pin.
#0
1
TPM0 external clock driven by TPM_CLKIN1 pin.
#1
TPM1CH0SRC
TPM1 channel 0 input capture source select
18
1
read-write
0
TPM1_CH0 signal
#0
1
CMP0 output
#1
TPM1CLKSEL
TPM1 External Clock Pin Select
25
1
read-write
0
TPM1 external clock driven by TPM_CLKIN0 pin.
#0
1
TPM1 external clock driven by TPM_CLKIN1 pin.
#1
SOPT5
System Options Register 5
0x1010
32
read-write
n
0x0
0x0
RESERVED
no description available
1
1
read-only
RESERVED
no description available
3
1
read-only
RESERVED
no description available
4
3
read-only
RESERVED
no description available
7
9
read-only
RESERVED
no description available
17
1
read-only
RESERVED
no description available
18
1
read-only
RESERVED
no description available
19
1
read-only
RESERVED
no description available
20
12
read-only
UART0ODE
UART0 Open Drain Enable
16
1
read-write
0
Open drain is disabled on UART0
#0
1
Open drain is enabled on UART0
#1
UART0RXSRC
UART0 receive data source select
2
1
read-write
0
UART0_RX pin
#0
1
CMP0 output
#1
UART0TXSRC
UART0 transmit data source select
0
1
read-write
0
UART0_TX pin
#0
1
UART0_TX pin modulated with TPM1 channel 0 output
#1
SOPT7
System Options Register 7
0x1018
32
read-write
n
0x0
0x0
ADC0ALTTRGEN
ADC0 alternate trigger enable
7
1
read-write
0
TPM1 channel 0 (A) and channel 1 (B) triggers selected for ADC0.
#0
1
Alternate trigger selected for ADC0.
#1
ADC0PRETRGSEL
ADC0 pretrigger select
4
1
read-write
0
Pre-trigger A
#0
1
Pre-trigger B
#1
ADC0TRGSEL
ADC0 trigger select
0
4
read-write
0000
External trigger pin input (EXTRG_IN)
#0000
0001
CMP0 output
#0001
0010
Reserved
#0010
0011
Reserved
#0011
0100
PIT trigger 0
#0100
0101
PIT trigger 1
#0101
0110
Reserved
#0110
0111
Reserved
#0111
1000
TPM0 overflow
#1000
1001
TPM1 overflow
#1001
1010
Reserved
#1010
1011
Reserved
#1011
1100
RTC alarm
#1100
1101
RTC seconds
#1101
1110
LPTMR0 trigger
#1110
1111
Reserved
#1111
RESERVED
no description available
5
2
read-only
RESERVED
no description available
8
24
read-only
SRVCOP
Service COP Register
0x1104
32
write-only
n
0x0
0x0
RESERVED
no description available
8
24
write-only
SRVCOP
Sevice COP Register
0
8
write-only
UIDL
Unique Identification Register Low
0x1060
32
read-only
n
0x0
0x0
UID
Unique Identification
0
32
read-only
UIDMH
Unique Identification Register Mid-High
0x1058
32
read-only
n
0x0
0x0
RESERVED
no description available
16
16
read-only
UID
Unique Identification
0
16
read-only
UIDML
Unique Identification Register Mid Low
0x105C
32
read-only
n
0x0
0x0
UID
Unique Identification
0
32
read-only
SMC
System Mode Controller
SMC
0x0
0x0
0x4
registers
n
PMCTRL
Power Mode Control register
0x1
8
read-write
n
0x0
0x0
RESERVED
no description available
4
1
read-only
RESERVED
no description available
7
1
read-only
RUNM
Run Mode Control
5
2
read-write
00
Normal Run mode (RUN)
#00
01
Reserved
#01
10
Very-Low-Power Run mode (VLPR)
#10
11
Reserved
#11
STOPA
Stop Aborted
3
1
read-only
0
The previous stop mode entry was successsful.
#0
1
The previous stop mode entry was aborted.
#1
STOPM
Stop Mode Control
0
3
read-write
000
Normal Stop (STOP)
#000
001
Reserved
#001
010
Very-Low-Power Stop (VLPS)
#010
011
Low-Leakage Stop (LLS)
#011
100
Very-Low-Leakage Stop (VLLSx)
#100
101
Reserved
#101
110
Reseved
#110
111
Reserved
#111
PMPROT
Power Mode Protection register
0x0
8
read-write
n
0x0
0x0
ALLS
Allow Low-Leakage Stop Mode
3
1
read-write
0
LLS is not allowed
#0
1
LLS is allowed
#1
AVLLS
Allow Very-Low-Leakage Stop Mode
1
1
read-write
0
Any VLLSx mode is not allowed
#0
1
Any VLLSx mode is allowed
#1
AVLP
Allow Very-Low-Power Modes
5
1
read-write
0
VLPR, VLPW and VLPS are not allowed
#0
1
VLPR, VLPW and VLPS are allowed
#1
RESERVED
no description available
0
1
read-only
RESERVED
no description available
2
1
read-only
RESERVED
no description available
4
1
read-only
RESERVED
no description available
6
2
read-only
PMSTAT
Power Mode Status register
0x3
8
read-only
n
0x0
0x0
PMSTAT
no description available
0
7
read-only
RESERVED
no description available
7
1
read-only
STOPCTRL
Stop Control Register
0x2
8
read-write
n
0x0
0x0
PORPO
POR Power Option
5
1
read-write
0
POR detect circuit is enabled in VLLS0
#0
1
POR detect circuit is disabled in VLLS0
#1
PSTOPO
Partial Stop Option
6
2
read-write
00
STOP - Normal Stop mode
#00
01
PSTOP1 - Partial Stop with both system and bus clocks disabled
#01
10
PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
#10
11
Reserved
#11
RESERVED
no description available
3
1
read-only
RESERVED
no description available
4
1
read-only
VLLSM
VLLS Mode Control.
0
3
read-write
000
VLLS0
#000
001
VLLS1
#001
010
Reserved
#010
011
VLLS3
#011
100
Reserved
#100
101
Reserved
#101
110
Reserved
#110
111
Reserved
#111
SPI0
Serial Peripheral Interface
SPI0
0x0
0x0
0x8
registers
n
SPI0
10
INT_SPI0
10
BR
SPI baud rate register
0x2
8
read-write
n
0x0
0x0
RESERVED
no description available
7
1
read-only
SPPR
SPI baud rate prescale divisor
4
3
read-write
000
Baud rate prescaler divisor is 1
#000
001
Baud rate prescaler divisor is 2
#001
010
Baud rate prescaler divisor is 3
#010
011
Baud rate prescaler divisor is 4
#011
100
Baud rate prescaler divisor is 5
#100
101
Baud rate prescaler divisor is 6
#101
110
Baud rate prescaler divisor is 7
#110
111
Baud rate prescaler divisor is 8
#111
SPR
SPI baud rate divisor
0
4
read-write
0000
Baud rate divisor is 2
#0000
0001
Baud rate divisor is 4
#0001
0010
Baud rate divisor is 8
#0010
0011
Baud rate divisor is 16
#0011
0100
Baud rate divisor is 32
#0100
0101
Baud rate divisor is 64
#0101
0110
Baud rate divisor is 128
#0110
0111
Baud rate divisor is 256
#0111
1000
Baud rate divisor is 512
#1000
C1
SPI control register 1
0x0
8
read-write
n
0x0
0x0
CPHA
Clock phase
2
1
read-write
0
First edge on SPSCK occurs at the middle of the first cycle of a data transfer
#0
1
First edge on SPSCK occurs at the start of the first cycle of a data transfer
#1
CPOL
Clock polarity
3
1
read-write
0
Active-high SPI clock (idles low)
#0
1
Active-low SPI clock (idles high)
#1
LSBFE
LSB first (shifter direction)
0
1
read-write
0
SPI serial data transfers start with most significant bit
#0
1
SPI serial data transfers start with least significant bit
#1
MSTR
Master/slave mode select
4
1
read-write
0
SPI module configured as a slave SPI device
#0
1
SPI module configured as a master SPI device
#1
SPE
SPI system enable
6
1
read-write
0
SPI system inactive
#0
1
SPI system enabled
#1
SPIE
SPI interrupt enable: for SPRF and MODF
7
1
read-write
0
Interrupts from SPRF and MODF are inhibited-use polling
#0
1
Request a hardware interrupt when SPRF or MODF is 1
#1
SPTIE
SPI transmit interrupt enable
5
1
read-write
0
Interrupts from SPTEF inhibited (use polling)
#0
1
When SPTEF is 1, hardware interrupt requested
#1
SSOE
Slave select output enable
1
1
read-write
0
When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input.
#0
1
When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.
#1
C2
SPI control register 2
0x1
8
read-write
n
0x0
0x0
BIDIROE
Bidirectional mode output enable
3
1
read-write
0
Output driver disabled so SPI data I/O pin acts as an input
#0
1
SPI I/O pin enabled as an output
#1
MODFEN
Master mode-fault function enable
4
1
read-write
0
Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
#0
1
Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
#1
RESERVED
no description available
6
1
read-only
RXDMAE
Receive DMA enable
2
1
read-write
0
DMA request for receive is disabled and interrupt from SPRF is allowed
#0
1
DMA request for receive is enabled and interrupt from SPRF is disabled
#1
SPC0
SPI pin control 0
0
1
read-write
0
SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in.
#0
1
SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI.
#1
SPISWAI
SPI stop in wait mode
1
1
read-write
0
SPI clocks continue to operate in wait mode
#0
1
SPI clocks stop when the MCU enters wait mode
#1
SPMIE
SPI match interrupt enable
7
1
read-write
0
Interrupts from SPMF inhibited (use polling)
#0
1
When SPMF is 1, requests a hardware interrupt
#1
TXDMAE
Transmit DMA enable
5
1
read-write
0
DMA request for transmit is disabled and interrupt from SPTEF is allowed
#0
1
DMA request for transmit is enabled and interrupt from SPTEF is disabled
#1
D
SPI data register
0x5
8
read-write
n
0x0
0x0
Bits
Data (low byte)
0
8
read-write
M
SPI match register
0x7
8
read-write
n
0x0
0x0
Bits
Hardware compare value (low byte)
0
8
read-write
S
SPI status register
0x3
8
read-only
n
0x0
0x0
MODF
Master mode fault flag
4
1
read-only
0
No mode fault error
#0
1
Mode fault error detected
#1
RESERVED
no description available
0
4
read-only
SPMF
SPI match flag
6
1
read-only
0
Value in the receive data buffer does not match the value in the M register
#0
1
Value in the receive data buffer matches the value in the M register
#1
SPRF
SPI read buffer full flag
7
1
read-only
0
No data available in the receive data buffer
#0
1
Data available in the receive data buffer
#1
SPTEF
SPI transmit buffer empty flag
5
1
read-only
0
SPI transmit buffer not empty
#0
1
SPI transmit buffer empty
#1
SystemControl
System Control Registers
SystemControl
0x0
0x8
0xD2C
registers
n
SCB_ACTLR
Auxiliary Control Register,
0x8
32
read-only
n
0x0
0x0
SCB_AIRCR
Application Interrupt and Reset Control Register
0xD0C
32
read-write
n
0x0
0x0
ENDIANNESS
no description available
15
1
read-only
0
Little-endian
#0
1
Big-endian
#1
SYSRESETREQ
no description available
2
1
write-only
0
no system reset request
#0
1
asserts a signal to the outer system that requests a reset
#1
VECTCLRACTIVE
no description available
1
1
write-only
VECTKEY
Register key
16
16
read-write
SCB_CCR
Configuration and Control Register
0xD14
32
read-only
n
0x0
0x0
STKALIGN
Indicates stack alignment on exception entry
9
1
read-only
UNALIGN_TRP
Always reads as one, indicates that all unaligned accesses generate a HardFault
3
1
read-only
SCB_CPUID
CPUID Base Register
0xD00
32
read-only
n
0x0
0x0
IMPLEMENTER
Implementer code
24
8
read-only
PARTNO
Indicates part number
4
12
read-only
REVISION
Indicates patch release: 0x0 = Patch 0
0
4
read-only
VARIANT
Indicates processor revision: 0x2 = Revision 2
20
4
read-only
SCB_DFSR
Debug Fault Status Register
0xD30
32
read-write
n
0x0
0x0
BKPT
no description available
1
1
read-write
0
No current breakpoint debug event
#0
1
At least one current breakpoint debug event
#1
DWTTRAP
no description available
2
1
read-write
0
No current debug events generated by the DWT
#0
1
At least one current debug event generated by the DWT
#1
EXTERNAL
no description available
4
1
read-write
0
No EDBGRQ debug event
#0
1
EDBGRQ debug event
#1
HALTED
no description available
0
1
read-write
0
No active halt request debug event
#0
1
Halt request debug event active
#1
VCATCH
no description available
3
1
read-write
0
No Vector catch triggered
#0
1
Vector catch triggered
#1
SCB_ICSR
Interrupt Control and State Register
0xD04
32
read-write
n
0x0
0x0
NMIPENDSET
no description available
31
1
read-write
0
write: no effect; read: NMI exception is not pending
#0
1
write: changes NMI exception state to pending; read: NMI exception is pending
#1
PENDSTCLR
no description available
25
1
write-only
0
no effect
#0
1
removes the pending state from the SysTick exception
#1
PENDSTSET
no description available
26
1
read-write
0
write: no effect; read: SysTick exception is not pending
#0
1
write: changes SysTick exception state to pending; read: SysTick exception is pending
#1
PENDSVCLR
no description available
27
1
write-only
0
no effect
#0
1
removes the pending state from the PendSV exception
#1
PENDSVSET
no description available
28
1
read-write
0
write: no effect; read: PendSV exception is not pending
#0
1
write: changes PendSV exception state to pending; read: PendSV exception is pending
#1
VECTPENDING
Exception number of the highest priority pending enabled exception
12
6
read-only
SCB_SCR
System Control Register
0xD10
32
read-write
n
0x0
0x0
SEVONPEND
no description available
4
1
read-write
0
only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
#0
1
enabled events and all interrupts, including disabled interrupts, can wakeup the processor
#1
SLEEPDEEP
no description available
2
1
read-write
0
sleep
#0
1
deep sleep
#1
SLEEPONEXIT
no description available
1
1
read-write
0
do not sleep when returning to Thread mode
#0
1
enter sleep, or deep sleep, on return from an ISR
#1
SCB_SHCSR
System Handler Control and State Register
0xD24
32
read-write
n
0x0
0x0
SVCALLPENDED
no description available
15
1
read-write
0
exception is not pending
#0
1
exception is pending
#1
SCB_SHPR2
System Handler Priority Register 2
0xD1C
32
read-write
n
0x0
0x0
PRI_11
Priority of system handler 11, SVCall
30
2
read-write
SCB_SHPR3
System Handler Priority Register 3
0xD20
32
read-write
n
0x0
0x0
PRI_14
Priority of system handler 14, PendSV
22
2
read-write
PRI_15
Priority of system handler 15, SysTick exception
30
2
read-write
SCB_VTOR
Vector Table Offset Register
0xD08
32
read-write
n
0x0
0x0
TBLOFF
Vector table base offset
7
25
read-write
SysTick
System timer
SysTick
0x0
0x0
0x10
registers
n
SYST_CALIB
SysTick Calibration Value Register
0xC
32
read-only
n
0x0
0x0
NOREF
no description available
31
1
read-only
0
The reference clock is provided
#0
1
The reference clock is not provided
#1
SKEW
no description available
30
1
read-only
0
10ms calibration value is exact
#0
1
10ms calibration value is inexact, because of the clock frequency
#1
TENMS
Reload value to use for 10ms timing
0
24
read-only
SYST_CSR
SysTick Control and Status Register
0x0
32
read-write
n
0x0
0x0
CLKSOURCE
no description available
2
1
read-write
0
external clock
#0
1
processor clock
#1
COUNTFLAG
no description available
16
1
read-write
ENABLE
no description available
0
1
read-write
0
counter disabled
#0
1
counter enabled
#1
TICKINT
no description available
1
1
read-write
0
counting down to 0 does not assert the SysTick exception request
#0
1
counting down to 0 asserts the SysTick exception request
#1
SYST_CVR
SysTick Current Value Register
0x8
32
read-write
n
0x0
0x0
CURRENT
Current value at the time the register is accessed
0
24
read-write
SYST_RVR
SysTick Reload Value Register
0x4
32
read-write
n
0x0
0x0
RELOAD
Value to load into the SysTick Current Value Register when the counter reaches 0
0
24
read-write
TPM0
Timer/PWM Module
TPM
0x0
0x0
0x88
registers
n
TPM0
17
INT_TPM0
17
C0SC
Channel (n) Status and Control
0x18
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts.
#0
1
Enable channel interrupts.
#1
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
RESERVED
no description available
1
1
read-only
RESERVED
no description available
8
24
read-only
C0V
Channel (n) Value
0x20
32
read-write
n
0x0
0x0
RESERVED
no description available
16
16
read-only
VAL
Channel Value
0
16
read-write
C1SC
Channel (n) Status and Control
0x2C
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts.
#0
1
Enable channel interrupts.
#1
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
RESERVED
no description available
1
1
read-only
RESERVED
no description available
8
24
read-only
C1V
Channel (n) Value
0x38
32
read-write
n
0x0
0x0
RESERVED
no description available
16
16
read-only
VAL
Channel Value
0
16
read-write
C2SC
Channel (n) Status and Control
0x48
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts.
#0
1
Enable channel interrupts.
#1
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
RESERVED
no description available
1
1
read-only
RESERVED
no description available
8
24
read-only
C2V
Channel (n) Value
0x58
32
read-write
n
0x0
0x0
RESERVED
no description available
16
16
read-only
VAL
Channel Value
0
16
read-write
C3SC
Channel (n) Status and Control
0x6C
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts.
#0
1
Enable channel interrupts.
#1
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
RESERVED
no description available
1
1
read-only
RESERVED
no description available
8
24
read-only
C3V
Channel (n) Value
0x80
32
read-write
n
0x0
0x0
RESERVED
no description available
16
16
read-only
VAL
Channel Value
0
16
read-write
C4SC
Channel (n) Status and Control
0x98
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts.
#0
1
Enable channel interrupts.
#1
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
RESERVED
no description available
1
1
read-only
RESERVED
no description available
8
24
read-only
C4V
Channel (n) Value
0xB0
32
read-write
n
0x0
0x0
RESERVED
no description available
16
16
read-only
VAL
Channel Value
0
16
read-write
C5SC
Channel (n) Status and Control
0xCC
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts.
#0
1
Enable channel interrupts.
#1
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
RESERVED
no description available
1
1
read-only
RESERVED
no description available
8
24
read-only
C5V
Channel (n) Value
0xE8
32
read-write
n
0x0
0x0
RESERVED
no description available
16
16
read-only
VAL
Channel Value
0
16
read-write
CNT
Counter
0x4
32
read-write
n
0x0
0x0
COUNT
Counter value
0
16
read-write
RESERVED
no description available
16
16
read-only
CONF
Configuration
0x84
32
read-write
n
0x0
0x0
CROT
Counter Reload On Trigger
18
1
read-write
0
Counter is not reloaded due to a rising edge on the selected input trigger
#0
1
Counter is reloaded when a rising edge is detected on the selected input trigger
#1
CSOO
Counter Stop On Overflow
17
1
read-write
0
LPTPM counter continues incrementing or decrementing after overflow
#0
1
LPTPM counter stops incrementing or decrementing after overflow.
#1
CSOT
Counter Start on Trigger
16
1
read-write
0
LPTPM counter starts to increment immediately, once it is enabled.
#0
1
LPTPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.
#1
DBGMODE
Debug Mode
6
2
read-write
00
LPTPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.
#00
11
LPTPM counter continues in debug mode.
#11
DOZEEN
Doze Enable
5
1
read-write
0
Internal LPTPM counter continues in Doze mode.
#0
1
Internal LPTPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.
#1
GTBEEN
Global time base enable
9
1
read-write
0
All channels use the internally generated LPTPM counter as their timebase
#0
1
All channels use an externally generated global timebase as their timebase
#1
RESERVED
no description available
0
5
read-only
RESERVED
no description available
8
1
read-only
RESERVED
no description available
10
6
read-only
RESERVED
no description available
19
5
read-only
RESERVED
no description available
28
4
read-only
TRGSEL
Trigger Select
24
4
read-write
MOD
Modulo
0x8
32
read-write
n
0x0
0x0
MOD
Modulo value
0
16
read-write
RESERVED
no description available
16
16
read-only
SC
Status and Control
0x0
32
read-write
n
0x0
0x0
CMOD
Clock Mode Selection
3
2
read-write
00
LPTPM counter is disabled
#00
01
LPTPM counter increments on every LPTPM counter clock
#01
10
LPTPM counter increments on rising edge of LPTPM_EXTCLK synchronized to the LPTPM counter clock
#10
11
Reserved
#11
CPWMS
Center-aligned PWM Select
5
1
read-write
0
LPTPM counter operates in up counting mode.
#0
1
LPTPM counter operates in up-down counting mode.
#1
DMA
DMA Enable
8
1
read-write
0
Disables DMA transfers.
#0
1
Enables DMA transfers.
#1
PS
Prescale Factor Selection
0
3
read-write
000
Divide by 1
#000
001
Divide by 2
#001
010
Divide by 4
#010
011
Divide by 8
#011
100
Divide by 16
#100
101
Divide by 32
#101
110
Divide by 64
#110
111
Divide by 128
#111
RESERVED
no description available
9
23
read-only
TOF
Timer Overflow Flag
7
1
read-write
0
LPTPM counter has not overflowed.
#0
1
LPTPM counter has overflowed.
#1
TOIE
Timer Overflow Interrupt Enable
6
1
read-write
0
Disable TOF interrupts. Use software polling or DMA request.
#0
1
Enable TOF interrupts. An interrupt is generated when TOF equals one.
#1
STATUS
Capture and Compare Status
0x50
32
read-write
n
0x0
0x0
CH0F
Channel 0 Flag
0
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH1F
Channel 1 Flag
1
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH2F
Channel 2 Flag
2
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH3F
Channel 3 Flag
3
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH4F
Channel 4 Flag
4
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH5F
Channel 5 Flag
5
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
RESERVED
no description available
6
2
read-only
RESERVED
no description available
9
23
read-only
TOF
Timer Overflow Flag
8
1
read-write
0
LPTPM counter has not overflowed.
#0
1
LPTPM counter has overflowed.
#1
TPM1
Timer/PWM Module
TPM
0x0
0x0
0x88
registers
n
TPM1
18
INT_TPM1
18
C0SC
Channel (n) Status and Control
0x18
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts.
#0
1
Enable channel interrupts.
#1
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
RESERVED
no description available
1
1
read-only
RESERVED
no description available
8
24
read-only
C0V
Channel (n) Value
0x20
32
read-write
n
0x0
0x0
RESERVED
no description available
16
16
read-only
VAL
Channel Value
0
16
read-write
C1SC
Channel (n) Status and Control
0x2C
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts.
#0
1
Enable channel interrupts.
#1
DMA
DMA Enable
0
1
read-write
0
Disable DMA transfers.
#0
1
Enable DMA transfers.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
RESERVED
no description available
1
1
read-only
RESERVED
no description available
8
24
read-only
C1V
Channel (n) Value
0x38
32
read-write
n
0x0
0x0
RESERVED
no description available
16
16
read-only
VAL
Channel Value
0
16
read-write
CNT
Counter
0x4
32
read-write
n
0x0
0x0
COUNT
Counter value
0
16
read-write
RESERVED
no description available
16
16
read-only
CONF
Configuration
0x84
32
read-write
n
0x0
0x0
CROT
Counter Reload On Trigger
18
1
read-write
0
Counter is not reloaded due to a rising edge on the selected input trigger
#0
1
Counter is reloaded when a rising edge is detected on the selected input trigger
#1
CSOO
Counter Stop On Overflow
17
1
read-write
0
LPTPM counter continues incrementing or decrementing after overflow
#0
1
LPTPM counter stops incrementing or decrementing after overflow.
#1
CSOT
Counter Start on Trigger
16
1
read-write
0
LPTPM counter starts to increment immediately, once it is enabled.
#0
1
LPTPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.
#1
DBGMODE
Debug Mode
6
2
read-write
00
LPTPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.
#00
11
LPTPM counter continues in debug mode.
#11
DOZEEN
Doze Enable
5
1
read-write
0
Internal LPTPM counter continues in Doze mode.
#0
1
Internal LPTPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.
#1
GTBEEN
Global time base enable
9
1
read-write
0
All channels use the internally generated LPTPM counter as their timebase
#0
1
All channels use an externally generated global timebase as their timebase
#1
RESERVED
no description available
0
5
read-only
RESERVED
no description available
8
1
read-only
RESERVED
no description available
10
6
read-only
RESERVED
no description available
19
5
read-only
RESERVED
no description available
28
4
read-only
TRGSEL
Trigger Select
24
4
read-write
MOD
Modulo
0x8
32
read-write
n
0x0
0x0
MOD
Modulo value
0
16
read-write
RESERVED
no description available
16
16
read-only
SC
Status and Control
0x0
32
read-write
n
0x0
0x0
CMOD
Clock Mode Selection
3
2
read-write
00
LPTPM counter is disabled
#00
01
LPTPM counter increments on every LPTPM counter clock
#01
10
LPTPM counter increments on rising edge of LPTPM_EXTCLK synchronized to the LPTPM counter clock
#10
11
Reserved
#11
CPWMS
Center-aligned PWM Select
5
1
read-write
0
LPTPM counter operates in up counting mode.
#0
1
LPTPM counter operates in up-down counting mode.
#1
DMA
DMA Enable
8
1
read-write
0
Disables DMA transfers.
#0
1
Enables DMA transfers.
#1
PS
Prescale Factor Selection
0
3
read-write
000
Divide by 1
#000
001
Divide by 2
#001
010
Divide by 4
#010
011
Divide by 8
#011
100
Divide by 16
#100
101
Divide by 32
#101
110
Divide by 64
#110
111
Divide by 128
#111
RESERVED
no description available
9
23
read-only
TOF
Timer Overflow Flag
7
1
read-write
0
LPTPM counter has not overflowed.
#0
1
LPTPM counter has overflowed.
#1
TOIE
Timer Overflow Interrupt Enable
6
1
read-write
0
Disable TOF interrupts. Use software polling or DMA request.
#0
1
Enable TOF interrupts. An interrupt is generated when TOF equals one.
#1
STATUS
Capture and Compare Status
0x50
32
read-write
n
0x0
0x0
CH0F
Channel 0 Flag
0
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH1F
Channel 1 Flag
1
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH2F
Channel 2 Flag
2
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH3F
Channel 3 Flag
3
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH4F
Channel 4 Flag
4
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH5F
Channel 5 Flag
5
1
read-write
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
RESERVED
no description available
6
2
read-only
RESERVED
no description available
9
23
read-only
TOF
Timer Overflow Flag
8
1
read-write
0
LPTPM counter has not overflowed.
#0
1
LPTPM counter has overflowed.
#1
UART0
Universal Asynchronous Receiver/Transmitter
UART0
0x0
0x0
0xC
registers
n
UART0
12
INT_UART0
12
BDH
UART Baud Rate Register High
0x0
8
read-write
n
0x0
0x0
LBKDIE
LIN Break Detect Interrupt Enable (for LBKDIF)
7
1
read-write
0
Hardware interrupts from UART _S2[LBKDIF] disabled (use polling).
#0
1
Hardware interrupt requested when UART _S2[LBKDIF] flag is 1.
#1
RXEDGIE
RX Input Active Edge Interrupt Enable (for RXEDGIF)
6
1
read-write
0
Hardware interrupts from UART _S2[RXEDGIF] disabled (use polling).
#0
1
Hardware interrupt requested when UART _S2[RXEDGIF] flag is 1.
#1
SBNS
Stop Bit Number Select
5
1
read-write
0
One stop bit.
#0
1
Two stop bit.
#1
SBR
Baud Rate Modulo Divisor.
0
5
read-write
BDL
UART Baud Rate Register Low
0x1
8
read-write
n
0x0
0x0
SBR
Baud Rate Modulo Divisor
0
8
read-write
C1
UART Control Register 1
0x2
8
read-write
n
0x0
0x0
DOZEEN
Doze Enable
6
1
read-write
0
UART is enabled in Wait mode.
#0
1
UART is disabled in Wait mode.
#1
ILT
Idle Line Type Select
2
1
read-write
0
Idle character bit count starts after start bit.
#0
1
Idle character bit count starts after stop bit.
#1
LOOPS
Loop Mode Select
7
1
read-write
0
Normal operation - UART _RX and UART _TX use separate pins.
#0
1
Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) UART _RX pin is not used by UART .
#1
M
9-Bit or 8-Bit Mode Select
4
1
read-write
0
Receiver and transmitter use 8-bit data characters.
#0
1
Receiver and transmitter use 9-bit data characters.
#1
PE
Parity Enable
1
1
read-write
0
No hardware parity generation or checking.
#0
1
Parity enabled.
#1
PT
Parity Type
0
1
read-write
0
Even parity.
#0
1
Odd parity.
#1
RSRC
Receiver Source Select
5
1
read-write
0
Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the UART _RX pins.
#0
1
Single-wire UART mode where the UART _TX pin is connected to the transmitter output and receiver input.
#1
WAKE
Receiver Wakeup Method Select
3
1
read-write
0
Idle-line wakeup.
#0
1
Address-mark wakeup.
#1
C2
UART Control Register 2
0x3
8
read-write
n
0x0
0x0
ILIE
Idle Line Interrupt Enable for IDLE
4
1
read-write
0
Hardware interrupts from IDLE disabled; use polling.
#0
1
Hardware interrupt requested when IDLE flag is 1.
#1
RE
Receiver Enable
2
1
read-write
0
Receiver disabled.
#0
1
Receiver enabled.
#1
RIE
Receiver Interrupt Enable for RDRF
5
1
read-write
0
Hardware interrupts from RDRF disabled; use polling.
#0
1
Hardware interrupt requested when RDRF flag is 1.
#1
RWU
Receiver Wakeup Control
1
1
read-write
0
Normal UART receiver operation.
#0
1
UART receiver in standby waiting for wakeup condition.
#1
SBK
Send Break
0
1
read-write
0
Normal transmitter operation.
#0
1
Queue break character(s) to be sent.
#1
TCIE
Transmission Complete Interrupt Enable for TC
6
1
read-write
0
Hardware interrupts from TC disabled; use polling.
#0
1
Hardware interrupt requested when TC flag is 1.
#1
TE
Transmitter Enable
3
1
read-write
0
Transmitter disabled.
#0
1
Transmitter enabled.
#1
TIE
Transmit Interrupt Enable for TDRE
7
1
read-write
0
Hardware interrupts from TDRE disabled; use polling.
#0
1
Hardware interrupt requested when TDRE flag is 1.
#1
C3
UART Control Register 3
0x6
8
read-write
n
0x0
0x0
FEIE
Framing Error Interrupt Enable
1
1
read-write
0
FE interrupts disabled; use polling.
#0
1
Hardware interrupt requested when FE is set.
#1
NEIE
Noise Error Interrupt Enable
2
1
read-write
0
NF interrupts disabled; use polling.
#0
1
Hardware interrupt requested when NF is set.
#1
ORIE
Overrun Interrupt Enable
3
1
read-write
0
OR interrupts disabled; use polling.
#0
1
Hardware interrupt requested when OR is set.
#1
PEIE
Parity Error Interrupt Enable
0
1
read-write
0
PF interrupts disabled; use polling).
#0
1
Hardware interrupt requested when PF is set.
#1
R8T9
Receive Bit 8 / Transmit Bit 9
7
1
read-write
R9T8
Receive Bit 9 / Transmit Bit 8
6
1
read-write
TXDIR
UART _TX Pin Direction in Single-Wire Mode
5
1
read-write
0
UART _TXD pin is an input in single-wire mode.
#0
1
UART _TXD pin is an output in single-wire mode.
#1
TXINV
Transmit Data Inversion
4
1
read-write
0
Transmit data not inverted.
#0
1
Transmit data inverted.
#1
C4
UART Control Register 4
0xA
8
read-write
n
0x0
0x0
M10
10-bit Mode select
5
1
read-write
0
Receiver and transmitter use 8-bit or 9-bit data characters.
#0
1
Receiver and transmitter use 10-bit data characters.
#1
MAEN1
Match Address Mode Enable 1
7
1
read-write
0
All data received is transferred to the data buffer if MAEN2 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.
#1
MAEN2
Match Address Mode Enable 2
6
1
read-write
0
All data received is transferred to the data buffer if MAEN1 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer.
#1
OSR
Over Sampling Ratio
0
5
read-write
C5
UART Control Register 5
0xB
8
read-write
n
0x0
0x0
BOTHEDGE
Both Edge Sampling
1
1
read-write
0
Receiver samples input data using the rising edge of the baud rate clock.
#0
1
Receiver samples input data using the rising and falling edge of the baud rate clock.
#1
RDMAE
Receiver Full DMA Enable
5
1
read-write
0
DMA request disabled.
#0
1
DMA request enabled.
#1
RESERVED
no description available
2
3
read-only
RESERVED
no description available
6
1
read-only
RESYNCDIS
Resynchronization Disable
0
1
read-write
0
Resynchronization during received data word is supported
#0
1
Resynchronization during received data word is disabled
#1
TDMAE
Transmitter DMA Enable
7
1
read-write
0
DMA request disabled.
#0
1
DMA request enabled.
#1
D
UART Data Register
0x7
8
read-write
n
0x0
0x0
R0T0
no description available
0
1
read-write
R1T1
no description available
1
1
read-write
R2T2
no description available
2
1
read-write
R3T3
no description available
3
1
read-write
R4T4
no description available
4
1
read-write
R5T5
no description available
5
1
read-write
R6T6
no description available
6
1
read-write
R7T7
no description available
7
1
read-write
MA1
UART Match Address Registers 1
0x8
8
read-write
n
0x0
0x0
MA
Match Address
0
8
read-write
MA2
UART Match Address Registers 2
0x9
8
read-write
n
0x0
0x0
MA
Match Address
0
8
read-write
S1
UART Status Register 1
0x4
8
read-write
n
0x0
0x0
FE
Framing Error Flag
1
1
read-write
0
No framing error detected. This does not guarantee the framing is correct.
#0
1
Framing error.
#1
IDLE
Idle Line Flag
4
1
read-write
0
No idle line detected.
#0
1
Idle line was detected.
#1
NF
Noise Flag
2
1
read-write
0
No noise detected.
#0
1
Noise detected in the received character in UART _D.
#1
OR
Receiver Overrun Flag
3
1
read-write
0
No overrun.
#0
1
Receive overrun (new UART data lost).
#1
PF
Parity Error Flag
0
1
read-write
0
No parity error.
#0
1
Parity error.
#1
RDRF
Receive Data Register Full Flag
5
1
read-only
0
Receive data buffer empty.
#0
1
Receive data buffer full.
#1
TC
Transmission Complete Flag
6
1
read-only
0
Transmitter active (sending data, a preamble, or a break).
#0
1
Transmitter idle (transmission activity complete).
#1
TDRE
Transmit Data Register Empty Flag
7
1
read-only
0
Transmit data buffer full.
#0
1
Transmit data buffer empty.
#1
S2
UART Status Register 2
0x5
8
read-write
n
0x0
0x0
BRK13
Break Character Generation Length
2
1
read-write
0
Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
#0
1
Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).
#1
LBKDE
LIN Break Detection Enable
1
1
read-write
0
Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
#0
1
Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).
#1
LBKDIF
LIN Break Detect Interrupt Flag
7
1
read-write
0
No LIN break character has been detected.
#0
1
LIN break character has been detected.
#1
MSBF
MSB First
5
1
read-write
0
LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
#0
1
MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M], C1[PE] and C4[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of C1[M] and C1[PE].
#1
RAF
Receiver Active Flag
0
1
read-only
0
UART receiver idle waiting for a start bit.
#0
1
UART receiver active ( UART _RXD input not idle).
#1
RWUID
Receive Wake Up Idle Detect
3
1
read-write
0
During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character.
#0
1
During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.
#1
RXEDGIF
UART _RX Pin Active Edge Interrupt Flag
6
1
read-write
0
No active edge on the receive pin has occurred.
#0
1
An active edge on the receive pin has occurred.
#1
RXINV
Receive Data Inversion
4
1
read-write
0
Receive data not inverted.
#0
1
Receive data inverted.
#1